UCS81003 datasheet(55/108 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005334A-page 55

UCS81003

10.4

Configuration Registers

The Configuration registers control basic device

functionality.

10.4.1

GENERAL CONFIGURATION

The contents of this register are retained in Sleep.

bit 1-0

PWR_STATE<1:0>: Indicates the current power state. These bits are set and cleared automatically as

the power state changes. (Note 1)

=Sleep

=Detect

=Active

Error

Note 1:

Accessing the SMBus/I2C causes the UCS81003 to leave the Sleep state. As a result, the

PWR_STATE<1:0> bits will never read as 00b.

PIN STATUS REGISTER (ADDRESS 14H) (CONTINUED)

Name

Bits

Address

Cof

Default

General Configuration

15h

R/W

01h

Emulation Configuration

16h

R/W

8Ch

Switch Configuration

17h

R/W

04h

Attach Detect Configuration

18h

R/W

46h

High-Speed Switch Configuration

25h

R/W

14h

GENERAL CONFIGURATION REGISTER (ADDRESS 15H)

R/W-0

U-x

R/W-0

R/W-1

ALERT_MASK

—

ALERT_LINK

DSCHG

RTN_EN

RTN_RST

RATION_BEH<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ALERT_MASK: Disables the ALERT# pin from asserting in the case of an error.

The ALERT# pin will not be asserted in the event of an error condition.

The ALERT# pin will be asserted if an error condition or indicator event is detected.

bit 6

Unimplemented

bit 5

ALERT_LINK: Links the ALERT# pin to be asserted when the LOW_CUR and/or TREG bits are set.

The ALERT# pin will be asserted if the LOW_CUR or TREG indicator bit is set.

The ALERT# pin will not be asserted if the LOW_CUR or TREG indicator bit is set.

bit 4

DSCHG: Forces the VBUS to be reset and discharged when the UCS81003 is in the Active state. Writing

this bit to a logic ‘1’ will cause the port power switch to be opened and the discharge circuitry to activate

to discharge VBUS. The port power switch will remain open while this bit is ‘1’. This bit is not self-clearing.

bit 3

RTN_EN: Ration Enable – enables charge rationing functionality and power monitoring.

Charge rationing is enabled (see Section 7.4 “Battery Full”).

Charge rationing is disabled. The Total Accumulated Charge registers will be cleared to 00_00h

and current data will no longer be accumulated. If the Total Accumulated Charge registers have

already reached the Charge Rationing Threshold (see Section 10.6 “Charge Rationing

Threshold Registers”), the applied response will be removed as if the charge rationing had

been reset. This will also clear the RATION status bit (if set).

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