UCS81003 datasheet(54/108 Pages) MICROCHIP

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UCS81003

DS20005334A-page 54

 2014 Microchip Technology Inc.

10.3.3

PIN STATUS REGISTER

The Pin Status register reflects the current pin state of

the external control pins as well as identifying the power

state. These bits are linked to the X_SET bits (see

Section 10.4.3 “Switch Configuration Register”).

bit 1

LG2: Indicates that the portable device successfully performed a handshake with the Legacy 2 charger emu-

lation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode

is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Lim-

iting Behavior Configuration Register”).

Handshake successful with the Legacy 2 charger emulation profile and charging.

Not charging with Legacy 2 charger emulation profile.

bit 0

LG1: Indicates that the portable device successfully performed a handshake with the Legacy 1 charger emu-

lation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see

Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode

is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Lim-

iting Behavior Configuration Register”).

Handshake successful with the Legacy 1 charger emulation profile and charging.

Not charging with Legacy 1 charger emulation profile.

PROFILE STATUS 2 REGISTER (ADDRESS 13H) (CONTINUED)

PIN STATUS REGISTER (ADDRESS 14H)

U-x

R-0

—

PWR_EN_PIN

M2_PIN

M1_PIN

EM_EN_PIN

SEL_PIN

PWR_STATE<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented

bit 6

PWR_EN_PIN: Reflects the PWR_EN control state. This bit is set and cleared automatically as the

PWR_EN pin/PWR_ENS bit state changes.

PWR_EN is Logic 1

PWR_EN is Logic 0

bit 5

M2_PIN: Reflects the M2 pin state. This bit is set and cleared automatically as the M2 pin/M2_SET

state changes.

M2 is Logic 1

M2 is Logic 0

bit 4

M1_PIN: Reflects the M1 pin state. This bit is set and cleared automatically as the M1 pin/M1_SET

state changes.

M1 is Logic 1

M1 is Logic 0

bit 3

EM_EN_PIN: Reflects the EM_EN pin state. This bit is set and cleared automatically as the EM_EN

pin/EM_EN_SET state changes.

EM_EN is Logic 1

EM_EN Logic 0

bit 2

SEL_PIN: Reflects the polarity settings determined by the SEL pin decode. This bit is set or cleared auto-

matically upon device power-up as the SEL pin is decoded.

= The PWR_EN control is active high

= The PWR_EN control is active low

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