TMS320C6472ECTZ datasheet(121/269 Pages) TI1

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TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

•

PTV15N - connect this pin to the 1.8-V supply via a 200-

Ω resistor.

When the RapidIO interface is not used, the CVDD2, AVDDA, DVDDD, DVDDR, and AVDDT pins can be NC or

connected directly to ground (VSS) to reduce power use. However, this prevents boundary-scan from

functioning on the RapidIO pins. To preserve boundary-scan functionality on the RapidIO pins CVDD2,

AVDDA, DVDDD, DVDDR, and AVDDT should be connected as follows:

•

CVDD2 - connect these pins to the 1.0/1.1-V core supply.

•

AVDDA, DVDDD, and AVDDT - connect these pins to the 1.2-V supply.

•

DVDDR - connect these pins to the 1.8-V supply.

7.4

Power and Sleep Controller (PSC)

The Power and Sleep Controller (PSC) controls TMS320C6472 device power by gating off clocks to

individual peripherals/modules. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs

(LPSCs). The GPSC contains memory mapped registers, power domain control, PSC interrupt control,

and a state machine for each peripheral/module. An LPSC is associated with each peripheral/module and

provides clock and reset control. The GPSC controls all of the TMS320C6472 LPSCs.

Figure 7-6 shows the PSC components and the power and clock domains they control. For more details

on the PSC, see the TMS320C6472/TMS320TCI6486 PSC User's Guide (literature number SPRUEG3).

C64x+ Peripheral Information and Electrical Specifications

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