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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320C6472ECTZ датащи(PDF) 37 Page - Texas Instruments |
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TMS320C6472ECTZ датащи(HTML) 37 Page - Texas Instruments |
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37 / 269 page  TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 Table 2-5. Terminal Functions (continued) SIGNAL TYPE(1) IPD/IPU(2) (3) DESCRIPTION NAME NO. JTAG EMULATION/TEST TCLK C27 I IPU JTAG test-port clock TDI D27 I IPU JTAG test-port data in TDO C29 O/Z IPU JTAG test-port data out TMS B28 I IPU JTAG test-port mode select JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see TRST C28 I IPD the IEEE 1149.1 JTAG compatibility statement portion of this data sheet. EMU0 A27 I/O/Z IPU Emulation pin 0 EMU1 D29 I/O/Z IPU Emulation pin 1 EMU2 D25 I/O/Z IPU Emulation pin 2 EMU3 D23 I/O/Z IPU Emulation pin 3 EMU4 C24 I/O/Z IPU Emulation pin 4 EMU5 C26 I/O/Z IPU Emulation pin 5 EMU6 E23 I/O/Z IPU Emulation pin 6 EMU7 D22 I/O/Z IPU Emulation pin 7 EMU8 D28 I/O/Z IPU Emulation pin 8 EMU9 B27 I/O/Z IPU Emulation pin 9 EMU10 E22 I/O/Z IPU Emulation pin 10 EMU11 E25 I/O/Z IPU Emulation pin 11 EMU12 A24 I/O/Z IPU Emulation pin 12 EMU13 D24 I/O/Z IPU Emulation pin 13 EMU14 C25 I/O/Z IPU Emulation pin 14 EMU15 B29 I/O/Z IPU Emulation pin 15 EMU16 D26 I/O/Z IPU Emulation pin 16 EMU17 E24 I/O/Z IPU Emulation pin 17 EMU18 A26 I/O/Z IPU Emulation pin 18 TELECOM SERIAL INTERFACE PORT 0 (TSIP0) CLKA0 U3 I IPD TSIP0 external clock A CLKB0 R4 I IPD TSIP0 external clock B FSA0 V2 I IPD TSIP0 frame sync A FSB0 Y1 I IPD TSIP0 frame sync B TR00 T3 TR01 U4 TR02 AA1 TR03 V1 I IPD TSIP0 receive data TR04 P5 TR05 R2 TR06 R3 TR07 U1 Copyright © 2009–2011, Texas Instruments Incorporated Device Overview 37 Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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