TMS320C6472ECTZ datasheet(16/269 Pages) TI1

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TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

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Table 2-3. Boot Mode Operation (continued)

BOOTMODE[3:0]

DESCRIPTION

TYPE

CFGGP[4:0]

CFGGP[4] =

PLLx10 mode of main PLLCTL is

selected

13 (1101)

RIO3

ROM

PLLx20 mode of main PLLCTL is

selected

CFGGP [3:0]: Node (1111b for default)

CFGGP[4] =

PLLx10 mode of main PLLCTL is

selected

14 (1110)

RIO4

ROM

PLLx20 mode of main PLLCTL is

selected

CFGGP [3:0]: Node (1111b for default)

15 (1111)

Reserved

ROM

Reserved

•

Immediate boot

When immediate boot is selected after global reset, the C64x+ megamodule core executes directly

from the internal L2 SRAM address programmed in the DSP_BOOT_ADDRx register. Note: device

operation is undefined if invalid code is address programmed in the DSP_BOOT_ADDRx register.

Executing invalid code may prevent connection by an emulator.

The default start addresses for megamodule core 0-5 boot are listed in Table 2-4.

Table 2-4. Megamodule Core 0-5 Boot Start Addresses

DEFAULT START

MEGAMODULE

ADDRESSES FOR

CORE NAME

DEVICE RESET/

LOCAL RESET

BOOT MODE 0-1

BOOT MODE 2-15

Megamodule

0x0080_0000

0x0010_0000

0x0010_0000, if the device

Core 0

reset was boot mode 2-15;

otherwise 0x0080_0000

Megamodule

0x0080_0000

Core 1

Megamodule

0x0080_0000

Core 2

Megamodule

0x0080_0000

Core 3

Megamodule

0x0080_0000

Core 4

Megamodule

0x0080_0000

Core 5

For boot mode 1, these addresses can be modifed by the host before it releases each megamodule

core from reset; for details, see Section 3.9.5. For boot mode 2-15, it is possible to have megamodule

core 0 modify the default address of megamodule core 1-5 before it releases each megamodule core

from reset; for details, see Section 2.4.1. For local reset, if all cores are required to begin from a

particular address, the default addresses have to be modified. One example is that only the

megamodule core 0's default address is modified to match megamodule core 1-5.

•

Host boot

If host boot is selected after global reset, all C64x+ megamodule cores are internally "held in reset"

while the remainder of the device (including all memory subsystems of the C64x+ megamodule) is

released from reset. During this period, an external host can initialize the C6472 device memory space

(shared memory as well as the C64x+ megamodule memory), as necessary through an HPI interface,

including internal configuration registers such as those that control the DDR2 or other peripherals.

Once the host is finished with all necessary initialization, it must write a 1 to bit fields BC0 through BC5

of the BOOT_COMPLETE_STAT register (inside the Boot Controller) indicating boot complete of the

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