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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320C6472ECTZ датащи(PDF) 99 Page - Texas Instruments |
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TMS320C6472ECTZ датащи(HTML) 99 Page - Texas Instruments |
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99 / 269 page  32Kbytes 32Kbytes 64Kbytes 128Kbytes 352Kbytes L2memory 00800000h 00858000h 00878000h 00888000h 00890000h 00898000h 11/19 SRAM 4-way cache 4-way cache 15/19 SRAM 4-way cache 17/19 SRAM 4-way 18/19 SRAM All SRAM 000 001 010 011 111 Blockbase address L2modebits TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C64x+ Megamodule. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset. Figure 5-4. TMS320C6472 L2 Memory Configurations For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's Guide (literature number SPRU862). All memory on the C6472 has a unique location in the memory map (see Table 2-2, C6472 Memory Map Summary). Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Megamodule 99 Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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