TMS320C6472ECTZ datasheet(63/269 Pages) TI1

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TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

3.3

Peripheral Selection After Device Reset

3.3.1

Controlling Internal Pulls on the Peripherals

3.3.1.1

Device Control Register (DEVCTL)

The device control register (DEVCTL) controls the internal pulls on the I/O interfaces. The bits are

initialized on the rising edge of the Power-On Reset from the GPIO pins [5:0], then software can override

these latched values. When the DSP is out of reset, the DEVCTL bits control the pullup and pulldown

resistors. When the DSP is held in reset, the GPIO pins enable the pullup and pulldown resistors, directly.

These bits also enable or disable the output buffers on these interfaces. When the pull-up or pull-down

resistors are enabled, the output buffers are disabled. When not in use, all the inputs should be in a

known state (i.e., needs to be internally pulled) and the corresponding I/O buffers should be powered

down to save I/O power. The DEVCTL register is shown in Figure 3-1 and described in Table 3-3.

Section 3.3.1.3 contains more detail about the operation of the internal resistor pulls and the output buffer

operation. It explicitly lists the relevant pins individually under all possible configurations and states

whether the output buffers are enabled or disabled and whether the internal pull resistors are enabled or

disabled.

Reserved

R-0000 0000

Reserved

EMAC1_EN

TSIP2_EN[2:0]

TSIP1_EN2

R/W-0

R/W-x

R/W-xxx

TSIP1_EN[1:0]

TSIP0_EN[2:0]

UTOPIA_EN[1:0]

HPI_EN

R/W-xxx

R/W-xx

R/W-x

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 3-1. Device Control Register (DEVCTL)

Table 3-3. Device Control Register (DEVCTL) Field Descriptions

Bit

Field

Value

Description

31:13

Reserved

EMAC1_EN

EMAC1 Internal Pulls Enable. Initialized at reset from GP05/EMAC1_EN pin.

Enable the pulls on the 3.3-V EMAC1 I/O pins and power down the corresponding I/O buffers. Also

disable the EMAC1 RGMII I/O pins.

Allow the pulls on the 3.3-V EMAC1 I/O to be disabled and the corresponding I/O buffers to be

powered up. Also allow the RGMII I/O buffers to be powered up. This input is combined with the

MACSEL1[1:0] configuration inputs to determine which I/O pins are enabled and which are

disabled. All disabled 3.3-V I/O pins will have internal pulls active.

TSIP2_EN[2]

TSIP2 Internal Pulls Enable[2]. Initialized at reset from GP04/TSIP2_EN pin.

Enable the pulls on TX[7:4] and TR[7:4] of the TSIP2 I/O pins and power down the corresponding

I/O buffers.

Disable the pulls on TX[7:4] and TR[7:4] of the TSIP2 I/O pins and power up the corresponding I/O

buffers.

TSIP2_EN[1]

TSIP2 Internal Pulls Enable[1]. Initialized at reset from GP04/TSIP2_EN pin.

Enable the pulls on TX[3:2] and TR[3:2] of the TSIP2 I/O pins and power down the corresponding

I/O buffers.

Disable the pulls on TX[3:2] and TR[3:2] of the TSIP2 I/O pins and power up the corresponding I/O

buffers.

Device Configuration

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