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TMS320C6472ECTZ датащи(PDF) 59 Page - Texas Instruments

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номер детали TMS320C6472ECTZ
подробное описание детали  TMS320C6472 Fixed-Point Digital Signal Processor
PDF  269 Pages
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TMS320C6472ECTZ датащи(HTML) 59 Page - Texas Instruments

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TMS320C6472
www.ti.com
SPRS612G
– JUNE 2009 – REVISED JULY 2011
3
Device Configuration
On the C6472 device, boot mode and certain device configurations/peripheral selections are determined
at device reset. Following device reset, the software needs to enable and configure the desired peripheral
modules.
3.1
Device Configuration at Device Reset
Table 3-1 describes the C6472 device configuration pins. The logic level of these pins is latched at reset
to determine the device configuration. The logic level on the device configuration pins can be set by using
external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive
these pins. When using a control device, care should be taken to ensure there is no contention on the
lines when the device is out of reset. The RESETSTAT pin can be monitored for this purpose. The device
configuration pins are sampled during reset and may be driven after the reset is removed. At this time, the
control device should ensure it has stopped driving the device configuration pins of the DSP to avoid
contention.
Table 3-1. C6472 Device Configuration Pins
CONFIGURATION
IPD/
NO.
FUNCTIONAL DESCRIPTION
PIN
IPU(1)
For more detailed information on the boot modes, see Section 2.4, Boot Mode
GP[9:6]_BOOTMODE[3:0]
IPU
Sequence, of this document.
Configuration GPI (General-Purpose Inputs for Configuration purposes
CFGGP[4:0])
GP[14:10]_CFGGP[4:0]
IPD
These pins are used in S/W routines located in internal ROM for boot operations.
For more detailed information on the use of the configuration pins for boot
operation, see Section 2.4, Boot Mode Sequence, of this document.
Enable SYSCLKOUT
GP[15]_SYSCLKOUTEN
IPD
0 - SYSCLKOUT is disabled (default)
1 - SYSCLKOUT is enabled
EMAC Interface selection for EMAC 1 (EMAC1_EN in the DEVCTL register must
be a 1 for these to be functional)
00 - Reserved
MACSEL1[1:0]
IPD
01 - SS-SMII (SS Mode)
10 - RGMII
11 - RMII
EMAC Interface selection for EMAC 0
000 - MII
001 - RMII
010 - GMII
MACSEL0[2:0]
IPD
011 - RGMII
100 - Reserved
101 - SS-SMII (SS Mode)
110 - Reserved
111 - Disabled
Device Endian mode (LENDIAN)
LENDIAN
IPU
0 - System operates in Big Endian mode
1 - System operates in Little Endian mode (default)
DDR2 Memory Controller enable (DDR2_EN)
0 - DDR2 Memory Controller module and pins are disabled (default)
DDREN
IPD
1 - DDR2 Memory Controller module and pins are enabled
Note that this is a static configuration input from reset.
RIOEN RapidIO enable
0 - RapidIO module and pins are disabled (default)
RIOEN
IPD
1 - RapidIO module and pins are enabled
Note that this is a static configuration input from reset.
(1)
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
Ω IPD or IPU resistor. To pull up a signal to the
opposite supply rail, a 1-k
Ω resistor should be used.)
Copyright
© 2009–2011, Texas Instruments Incorporated
Device Configuration
59
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