TMS320C6472ECTZ datasheet(60/269 Pages) TI1

60 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

3.1.1

Debugging Considerations

It is recommended that external connections be provided to device configuration pins, including all GPIO,

MACSEL, DDREN, and RIOEN pins. Although internal pullup/pulldown resistors exist on these pins,

providing external connectivity adds convenience to the user in debugging and flexibility in switching

operating modes. It also improves noise immunity for critical mode control inputs.

For the internal pullup/pulldown resistors for all device pins, see Table 2-5, Terminal Functions.

3.2

Device Configuration Register Descriptions

Table 3-2 is a summary of the primary chip-level registers that are discussed in Section 3.3 through

Section 3.11.

Table 3-2. Device Configuration Registers (Chip-Level Registers)

HEX ADDRESS RANGE

ACRONYM

COMMENTS

Provides status of the user's

02A8 0000

DEVSTAT

Device Status Register

device configuration on reset.

Sets DMA access priorities for

02A8 0004

PRI_ALLOC

Priority Allocation Register

master peripherals.

02A8 0008

DEVICE_ID

Device ID Register

Identifies the device.

02A8 000C - 02A8 01FC

Reserved

Controls the internal pulls on I/O

02A8 0200

DEVCTL

Device Control Register

interfaces.

This key register controls the

02A8 0204

DEVCTL_KEY

Device Control Key Register

writes to DEVCTL register. Key

value is 0A1E 183Ah.

02A8 0208

RMIIRESET0

RMII0 Reset Register

Provides reset to RMII. Used

when changing speed or duplex

02A8 020C

RMIIRESET1

RMII1 Reset Register

setting.

02A8 0210 - 02A8 0408

Reserved

This register configures privilege

02A8 040C

HOSTPRIV

Host Memory Privilege Register

modes.

02A8 0410 - 02A8 0418

Reserved

This register overrides the

02A8 041C

PRIVPERM

Memory Privilege Permission Register

memory protection for leaf node

in the CFG SCR.

This register is used for key

based protection of HOSTPRIV

02A8 0420

PRIVKEY

Memory Privilege Key Register

and PRIVPERM to control the

changes in the permission levels.

02A8 0424 - 02A8 04FC

Reserved

02A8 0500

NMIGR0

02A8 0504

NMIGR1

02A8 0508

NMIGR2

NMIGRx register creates NMI

NMI Generation Registers

event to C64x+ Megamodulex

02A8 050C

NMIGR3

02A8 0510

NMIGR4

02A8 0514

NMIGR5

02A8 0518 - 02A8 053C

Reserved

02A8 0540

IPCGR0

02A8 0544

IPCGR1

IPCGRx register generates an

02A8 0548

IPCGR2

IPC Generation Registers

interrupt pulse to C64x+

02A8 054C

IPCGR3

Megamodulex.

02A8 0550

IPCGR4

02A8 0554

IPCGR5

02A8 0558 - 02A8 0578

Reserved

Device Configuration

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