TMS320C6472ECTZ datasheet(120/269 Pages) TI1

120 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

Table 7-1. Timing Requirements for Power-Supply Sequence (Option 1)(1)

500/625/700

NO.

UNIT

MIN

MAX

tsu(DVDD33-CVDD)

Setup time, DVDD33 supply stable before CVDD supply stable

0.5

200

Setup time, CVDD supply stable before DVDD18 supply and VREFSSTL

tsu(CVDD-DVDD18)

200

reference voltage stable

Setup time, DVDD18 supply and VREFSSTL reference voltage stable before

tsu(DVDD18-DVDD15)

200

DVDD15 supply and VREFHSTL reference voltage stable

Setup time, DVDD15 supply and VREFHSTL reference voltage stable before

tsu(DVDD15-DVDD)

200

DVDD supply stable

(1)

Note: The word stable means voltages that have reached a valid level as described in .

Table 7-2. Timing Requirements for Power-Supply Sequence (Option 2)(1)

500/625/700

NO.

UNIT

MIN

MAX

tsu(DVDD33-CVDD)

Setup time, DVDD33 supply stable before CVDD supply stable

0.5

200

tsu(CVDD-ALLSUP)

Setup time, CVDD supply stable before all other supplies stable

200

(1)

Note: The word stable means voltages that have reached a valid level as described in .

For detailed information, see the TMS320C6472/TMS320TCI6486 Hardware Design Guide (literature

number SPRAAQ4).

7.3.2

Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as

possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum

distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a

yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling

capacitors, therefore physically smaller capacitors should be used while maintaining the largest available

capacitance value. As with the selection of any component, verification of capacitor availability over the

product's production lifetime should be considered.

7.3.3

Preserving Boundary-Scan Functionality on DDR2, RGMII, and RapidIO Interface Pins

When the DDR2 Memory Controller is not used, the DVDD18, DVDD18MON, VREFSSTL, AVDDA3, AVDDA4,

CVDD1, PTV18P, and PTV18N pins can be NC or connected directly to ground (VSS) to save power.

However, this prevents boundary scan from functioning on the DDR2 Memory Controller pins. To preserve

boundary-scan functionality on the DDR2 Memory Controller pins DVDD18, DVDD18MON, VREFSSTL, AVDDA3,

AVDDA4, CVDD1, PTV18P, and PTV18N should be connected as follows:

•

DVDD18, DVDD18MON, AVDDA3, and AVDDA4 - connect these pins to the 1.8-V supply.

•

CVDD1 - connect these pins to the 1.2-V supply.

•

VREFSSTL - connect this pin to a voltage of 0.9 V. This voltage can be generated directly from the 1.8-V

supply using two 1-k

Ω resistors to form a resistor-divider circuit.

•

PTV18P - connect this pin to ground (VSS) via a 200-Ω resistor.

•

PTV18N - connect this pin to the 1.8-V supply via a 200-

Ω resistor.

When the RGMII mode of the EMAC is not used, the DVDD15, DVDD15MON, VREFHSTL, PTV15P, and PTV15N

pins can be NC or connected directly to ground (VSS) to save power. However, this prevents boundary

scan from functioning on the RGMII pins of the EMAC. To preserve boundary-scan functionality on the

RGMII pins DVDD15, DVDD15MON, VREFHSTL, PTV15P, and PTV15N should be connected as follows:

•

DVDD15 and DVDD15MON - connect these pins to the 1.8-V supply.

•

VREFHSTL - connect to a voltage of 0.9 V. This voltage can be generated directly from the 1.8-V supply

using two 1-k

Ω resistors to form a resistor-divider circuit.

•

PTV15P - connect this pin to ground (VSS) via a 200-Ω resistor.

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C64x+ Peripheral Information and Electrical Specifications

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