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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320C6472ECTZ датащи(PDF) 32 Page - Texas Instruments |
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TMS320C6472ECTZ датащи(HTML) 32 Page - Texas Instruments |
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32 / 269 page  TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL TYPE(1) IPD/IPU(2) (3) DESCRIPTION NAME NO. BSDDQGATE3 E14 I/O/Z BSDDQGATE2 B16 I/O/Z DDR2 Memory Controller data strobe gate [3:0] BSDDQGATE1 D2 I/O/Z BSDDQGATE0 C2 I/O/Z RESETS External LRESET input pin to assert/de-assert LRESET to the LRESET J4 I IPU core specified by CORESEL[2:0] is latched when LRESETNMIEN is rising. External nonmaskable interrupt input to assert/de-assert NMI to NMI K2 I IPU the core specified by CORESEL[2:0] is latched when LRESETNMIEN is rising. CORESEL0 H3 I IPU Core Select input pins used to identify the designated megamodule(s) for LRESET or NMI CORESEL1 G3 I IPU 000 = C64x+ megamodule 0 001 = C64x+ megamodule 1 010 = C64x+ megamodule 2 011 = C64x+ megamodule 3 CORESEL2 G2 I IPU 100 = C64x+ megamodule 4 101 = C64x+ megamodule 5 110 = Reserved 111 = All C64x+ megamodules LRESET and NMI latch enable. The state of the LRESET and LRESETNMIEN J3 I IPU NMI inputs is latched to the selected megamodule(s) on the rising edge. RESET G1 I Device reset Reset status pin. The RESETSTAT output is active (low) when RESETSTAT J5 O IPU the device is in reset. Bootactive indication from the boot controller that boot is active BOOTACTIVE K1 O/Z IPU (see Section 3.9.2). POR H1 I Power-on reset PLL CLKIN1 K28 I IPD Clock input for PLL1 (core clock) CLKIN2 AH13 I IPD Clock input for PLL2 (EMAC clock) CLKIN3 A23 I IPD Clock input for PLL3 (DDR2 clock) SYSCLKOUT K27 O/Z IPU Clock output (PLL1 output clock/6) RAPIDIO RIOCLKP U25 I RapidIO serial port source (reference) clock positive/negative RIOCLKN T25 RIORXP0 P27 I RapidIO receive port 0 positive/negative (differential) RIORXN0 N27 RIORXP1 T29 I RapidIO receive port 1 positive/negative (differential) RIORXN1 U29 RIOTXP0 N29 O RapidIO transmit port 0 positive/negative (differential) RIOTXN0 P29 RIOTXP1 U27 O RapidIO transmit port 1 positive/negative (differential) RIOTXN1 T27 TIMERS Watchdog timer output (logical combination of six watchdog WDOUT H2 O/Z IPU timers) TIMI0 V28 I IPD Timer input pin TIMI1 V29 I IPD Timer input pin TIMO2 V27 O/Z IPD Timer output pin 32 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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