TMS320C6472ECTZ datasheet(114/269 Pages) TI1

114 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

6.2

Recommended Operating Conditions

(1)

PARAMETER

MIN

NOM

MAX UNIT

500 MHz

0.95

1.0

1.05

CVDD

Supply voltage, Core

625 MHz

1.05

1.1

1.16

700 MHz

1.14

1.2

1.26

500 MHz

0.95

1.0

1.05

CVDD2

Supply voltage, SRIO Core

625 MHz

1.05

1.1

1.16

700 MHz

1.14

1.2

1.26

CVDD1

Supply volttage, 1.2-V DDR Core

1.14

1.2

1.26

DVDD33

Supply voltage, 3.3-V I/O

3.135

3.3

3.465

DVDD18

Supply voltage, 1.8-V I/O (DDR)

1.71

1.8

1.89

DVDD15

Supply voltage, 1.8-V/1.5-V I/O (RGMII)

1.4

1.9

VREFHSTL

Reference voltage, RGMII I/O

0.7

0.95

(0.5 * DVDD15)

VREFSSTL

Reference voltage, DDR2 I/O

0.855

0.9

0.945

(0.5 * DVDD18)

AVDDA1

Analog supply voltage, PLL1 (System PLL)

1.71

1.8

1.89

AVDDA2

Analog supply voltage, PLL2 (EMAC PLL)

1.71

1.8

1.89

AVDDA3

Analog supply voltage, PLL3 (DDR PLL)

1.71

1.8

1.89

AVDDA4

Analog supply voltage, DDR

1.71

1.8

1.89

DVDDD

SRIO Digital supply voltage

1.14

1.2

1.26

AVDDA

SRIO Analog supply voltage

1.14

1.2

1.26

AVDDT

SRIO Termination voltage

1.14

1.2

1.26

DVDDR

SRIO Regulator supply voltage

1.35

1.5/1.8

1.98

3.3-V pins (except

2.0

DVDD33 + 0.5

I2C pins)

I2C pins

0.7 * DVDD33

DVDD33 + 0.5

VIH

High-level input voltage

RGMII pins

VREFHSTL + 0.10

DVDD15 + 0.3

DDR2 memory

VREFSSTL + 0.125

DVDD18 + 0.3

controller pins

3.3-V pins (except

-0.5

0.8

I2C pins)

I2C pins

-0.5

0.3 * DVDD33

VIL

Low-level input voltage

RGMII pins

-0.3

VREFHSTL - 0.1

DDR2 memory

-0.3

VREFSSTL - 0.125

controller pins

CVDD = CVDD2 =

1.0 V, CPU

2.38

frequency =

500 MHz

CVDD = CVDD2 =

1.1 V, CPU

PCDD

Core supply power(2)

3.76

frequency =

625 MHz

CVDD = CVDD2 =

1.2 V, CPU

5.42

frequency =

700 MHz

(1)

Operating conditions are at 500 MHz, 625 MHz, or 700 MHz.

(2)

Assumes the following conditions: CPU utilization 30% DSP/60% control; DDR2 at 30% utilization (266 MHz), 35% writes, 32 bits, 15%

bit switching; TSIP0, TSIP1, and TSIP2 at 20% utilization, 15% switching; UTOPIA 50 MHz, 16-bit at 50% utilization, 15% switching

EMAC0, 1000 Mbps, RGMII, 50% utilization, 50% switching; EMAC1 disabled; SRIO both lanes disabled; all timers active; HPI disabled;

I2C enabled at 10% utilization; room temperature (25

°C). The actual power consumption is application-dependent. For more details on

core and I/O activity, see the TMS320C6472/TMS320TCI6486 Power Consumption Summary (literature number SPRAAS4).

114

Device Operating Conditions

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