LP3913 datasheet(63/70 Pages) TI1

63 / 70 page

LP3913

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SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

Connect the buck ground and the ground of the capacitors together using generous component-side copper fill

as a pseudo-ground plane. Then connect this back to the general board system ground plane at a single point.

Place the pseudo-ground plane below these components and then have it tied to system ground of the output

capacitor outside of the current loops. This prevents the switched current from injecting noise into the system

ground. These components along with the inductor and output should be placed on the same side of the circuit

board, and their connections should be made on the same layer.

Route the noise sensitive traces such as the voltage feedback path away from the inductor. This is done by

routing it on the bottom layer or by adding a grounded copper area between switching node and feedback path.

Noisy traces between the power components and keep any digital lines away from this section. Keep the

feedback node as small as possible so that the ground pin and ground traces will shield it from the SW or buck

output.

Use wide traces between the power components and for power connections to the DC-DC converter circuit. This

reduces voltage errors caused by resistive losses.

Thermal Performance of the WQFN Package

The LP3913 is a monolithic device with integrated power FETs. For that reason, it is important to pay special

attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize

power dissipation of the WQFN package.

The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at

the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.

Compared to the traditional leaded packages where the die attach pad is embedded inside the molding

compound, the WQFN reduces one layer in the thermal path.

The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered

down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on

thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (

θJ) can be improved by a

factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land

and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer

diameter for thermal vias are 1.27 mm and 0.33 mm, respectively. Typical copper via barrel plating is 1 oz.,

although thicker copper may be used to further improve thermal performance. The LP3913 die attach pad is

connected to the substrate of the IC and therefore, the thermal land and vias on the PCB board need to be

connected to ground (GND pin).

For more information on board layout techniques, refer to Application Note AN-1187 Leadless Leadframe

Package (LLP) (SNOA401).

This application note also discusses package handling, solder stencil, and the assembly process.

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