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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP3913 датащи(PDF) 4 Page - Texas Instruments |
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LP3913 датащи(HTML) 4 Page - Texas Instruments |
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4 / 70 page  LP3913 SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013 www.ti.com Pin # Name I/O Type Functional Description 14 NRST O Open Open drain active low reset during Standby Drain 15 CHG O D This output indicates that a valid charger supply source (USB adapter) has been detected, and the IC is charging. (Red LED) 16 STAT O D Battery Status output indicator - Off during CC, 50% duty cycle during CV, 100% duty cycle with a fully charged Li-ion battery (Green LED) 17 BUCK1EN I D Digital input to enable/disable BUCK1 18 VFB1 I A Buck1 Feedback input terminal 19 BCKGND1 G G Buck1 Ground 20 VBUCK1 O A Buck1 Output 21 VIN2 I PWR Power input to BUCK1. VIN2 pin must be externally shorted to the VDD pins. 22 VIN3 I PWR Power input to BUCK2. VIN3 pin must be externally shorted to the VDD pins. 23 VBUCK2 O A Buck2 Output 24 BCKGND2 G G Buck2 Ground 25 VFB2 I A Buck2 Feedback input terminal 26 ONOFF I D Power ON/OFF pin configured either as level (High or Low) triggered or edge (High or Low) triggered. 27 I2C_SCL I D I2C-compatible interface clock terminal 28 VDDIO I D Supply to input / output stages of digital I/O 29 I2C_SDA I/O D I2C-compatible interface data terminal 30 ONSTAT O Open Open Drain output that reflects the debounced state of ONOFF pin. Drain 31 VFB3 I A Buck3 Feedback input terminal 32 VBUCK3 O A Buck3Output voltage 33 VBUCK3L2 I A Buck3 inductor 34 BCK3GND1 G G Buck3t high current ground 35 VBUCK3L1 I A Buck3 inductor 36 VIN4 I PWR Power input to Buck3. VIN4 pin must be externally shorted to the VDD pins. 37 USBSUSP I D This pin needs to be pulled high during USB suspend mode. 38 USBISEL I D Pulling this pin low limits the USB charge current to 100 mA. Pulling this pin high limits the USB charge current to 500 mA. 39 BUCK3GND2 G G Buck3 Core Ground 40 DGND G G Digital ground 41 VDD3 I PWR Power input to supply application. This pin must be externally shorted to VDD1 and VDD2. 42 VDD2 I PWR Power input to supply application This pin must be externally shorted to VDD1 and VDD3. 43 VBATT3 O A Positive battery terminal. This pin must be externally shorted to V\BATT1 and VBATT2. 44 VBATT2 O A Positive battery terminal. This pin must be externally shorted to VBATT1 and VBATT3. 45 USBPWR I PWR USB power input pin 46 VDD1 I PWR Power input to supply application This pin is shorted to VDD2 and VDD3. 47 CHG_DET I A Wall adapter power input pin 48 IREF I A A 121 k Ω resistor must be connected between this pin and AGND. The resistor value determines the reference current for the internal bias generator. A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3913 |
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