LP3913 datasheet(31/70 Pages) TI1

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ONSTAT

NRST

POWERACK deadline

VBUCK2

ONOFF

External

Events

128 ms

POWERACK

VREFH

(Bit D4 in PON register or

POWERBACK pin)

VBUCK3

VBUCK1

CHG_DET/USBPWR

(If LDO2ENB is logic 1 during NRST Low,

otherwise LDO2 are register or pin enabled)

VLDO1, VLDO2

60 ms

deglitch

32 ms

25 ms

20 ms

15 ms

5 ms

(To Microprocessor)

(From Microprocessor)

LP3913

www.ti.com

SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

Figure 56. Power Up Sequence

Transitioning From Active Mode To Standby Mode

External Event Triggers the Transition from Active to Standby Mode

When the device is active, a subsequent re-assertion of the push button will turn off the LP3913 indirectly by first

flagging the system processor though the ONSTAT pin. Upon detecting the ONSTAT transition, the system

processor must clear bit D4 (PACK) in the Power On Event Register and apply a logic low to the POWERACK

pin to power down the LP3913, which then transitions to Standby Mode. Clearing the PACK register bit and

POWERACK pin while external supply sources are present (either USB or CHG_IN) will not power down the

LP3913, to keep the charger active. The system can as always disable all necessary DC/DC converters, except

BUCK1, through the register control.

When external power is disconnected, LP3913 will remain in its Active state unless the battery voltage is below

VBLA (Battery Low Alarm) or unless the PACK (either bit D4 in the PON register and the POWERACK pin) is

cleared by the system processor.

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