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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP3913 датащи(PDF) 6 Page - Texas Instruments |
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LP3913 датащи(HTML) 6 Page - Texas Instruments |
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6 / 70 page  LP3913 SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013 www.ti.com GENERAL ELECTRICAL CHARACTERISTICS Unless otherwise noted, VDD = 5V, VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = 0°C to +125°C. (1) (2) (3) (4) Symbol Parameter Conditions Min Typ Max Units IQ_BATT Battery Standby Supply All circuits off except for Current POR and battery monitor. 6 20 µA No adapter or USB power connected. VPOR Power-On Reset Threshold VDD Falling Edge 1.9 V TSD Thermal Shutdown 160 °C Threshold TSDH Themal Shutdown 20 °C Hysteresis TTH-ALERT Thermal Interrupt 115 °C Threshold VDDIO IO Supply 2.5 VDD V FCLK Internal System Clock 2 MHz Frequency (1) All voltages are with respect to the potential at the GND pin. (2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm. (3) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. (4) Specified by design. Not production tested I 2C INTERFACE ELECTRICAL CHARACTERISTICS Unless otherwise noted, VDDIO = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = 0°C to +125°C. (1) (2) (3) (4) Symbol Parameter Conditions Min Typ Max Units VIL Low Level Input Voltage I2C_SDA & I2C_SCL 0.3VDDI V O VIH High Level Input Voltage I2C_SDA & I2C_SCL 0.7VDDI V O VOL Low Level Output Voltage I2C_SDA & I2C_SCL 0.2VDDI 0 V O VHYS Schmitt Trigger Input Hysterisis I2C_SDA & I2C_SCL 0.1VDDI V O FCLK Clock Frequency 400 kHz tBF Bus-Free Time between START (4) 1.3 µs and STOP tHOLD Hold Time Repeated START (4) 0.6 µs Condition tCLK-LP CLK Low Period (4) 1.3 µs tCLK-HP CLK High Period (4) 0.6 µs tSU Set-up Time Repeated START (4) 0.6 µs Condition tDATA-HOLD Data Hold Time (4) 0 µs tDATA-SU Data Set-up Time (4) 100 ns tSU Set-Up Time for STOP Condition (4) 0.6 µs tTRANS Maximum Pulse Width of Spikes (4) That Must Be Suppressed by the 50 µs Input Filter of Both Data and CLK Signals. (1) All voltages are with respect to the potential at the GND pin. (2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm. (3) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. (4) Specified by design. Not production tested. 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3913 |
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