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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP3913 датащи(PDF) 32 Page - Texas Instruments |
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LP3913 датащи(HTML) 32 Page - Texas Instruments |
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32 / 70 page  ONSTAT NRST ONOFF 3 ms POWERACK VREFH t0 64 ms 5 ms 5 ms 38 ms 43 ms 48 ms 58 ms t1 t2 t3 t4 t5 32 ms 32 ms deglitch deglitch (Bit D4 in PON register and POWERBACK pin) VBUCK3 VBUCK2 VBUCK1 VLDO1, VLDO2 (To Microprocessor) (From Microprocessor) LP3913 SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013 www.ti.com Figure 57. Power Down Caused by External Event Transition from Active to Standby Mode Due to Expiring POWERACK Deadline With no external charger present when the system processor fails to acknowledge the power-on in time by setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128 ms deadline following the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources will be disabled before transitioning to Standby Mode. This 2 ms delay allows the microprocessor to receive a clean reset before the power is de-asserted. A new power-on event is then required to transition back to Active mode. With either external charger present when the system processor fails to acknowledge the power-on in time by setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128 ms deadline following the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources will be disabled before transitioning to Charger Standby Mode. 32 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP3913 |
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