LP3913 datasheet(53/70 Pages) TI1

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VBUCK

VFB

Lsw

Csw

Cff

Load

BCKGND

LP3913

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SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

Figure 67. External Control of Buck Output Voltage through Feedback Resistor Ladder

BUCK1, BUCK2 Control Registers and BUCK1EN Pin

BUCK1 and BUCK2 are configurable through I2C accessible registers. Bit fields D4–0 control the output voltage.

Bit D5 defines the Modulation mode of the buck, which by default automatically selects PWM or PFM mode

depending on the load as described above in the functional description. The modulation mode can be forced to

PWM mode regardless of the load by setting bit D5 to a logic 1 in the corresponding buck control register.

Bit D6 controls the enable/disable state of the buck, which is different for BUCK1 and BUCK2 as BUCK1 has an

external enable pin: BUCK1EN.

For BUCK1, by default or when D6 is programmed logic 0 in the BUCK1 control register, enable/disable control

is passed onto the BUCK1EN pin. A logic 1 applied to this pin enables BUCK1 while a logic 0 disables BUCK1.

Setting D6 to 1 in the BUCK1 control register enables BUCK1, regardless of the state of the BUCK1EN pin. If the

system designer permanently connects the BUCK1EN pin to GND, then D6 is simply a enable/disable control bit.

If the system design permanently connects the enable pin to VDD, then the BUCK1 is enabled during the power-

on sequence and will always be on, regardless of the state of bit D6 in the BUCK1 control register (see Power

On/Off Sequencing).

BUCK2 is by default enabled during the power-on sequence and can be enabled/disabled through bit D6 in the

BUCK2 control register.

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