LP3913 datasheet(33/70 Pages) TI1

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ONSTAT

VBUCK1

NRST

PowerACK

VBUCK2

ONOFF

External Events

Power Down Caused by Expiring PowerACK deadline

(If LDO2ENB is logic 1 during NRST Low,

otherwise LDO2 are pin or register enabled)

VLDO1, VLDO2

VBUCK3

PowerACK deadline (expired)

CHG_DET/USBPWR

(From Microprocessor)

(Bit D4 in PON register and

POWERACK pin)

(To Microprocessor)

LP3913

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SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

Figure 58. Power Down Caused by Expiring PowerACK Deadline

Transition from Charger Standby Mode to Either Active or Standby Mode

While in Charger Standby mode, the battery is charged using the default values of IPROG, EOC, VTERM, Batt Temp

Range and USB ISEL. In Charger Standby mode, all the regulators and the I

2C are disabled. A new power-on

event is required to transition back to Active Mode. Removing the charger during Charger Standby Mode causes

a transition back to Standby Mode.

I2C-Compatible Serial Interface

I2C Signals

The LP3913 features an I2C compatible serial interface, using two dedicated pins: I2C_SCL and I2C_SDA for I2C

clock and data respectively. Both signals need a pull-up resistor according to the I2C specification. The LP3913

interface is an I2C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400 kbit/s. See

I2C specification from Philips for further details.

I2C Data Validity

The data on I2C_SDA line must be stable during the HIGH period of the clock signal (I2C_SCL), e.g., the state of

the data line can only be changed when CLK is LOW.

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