LP3913 datasheet(28/70 Pages) TI1

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Clock

Divider

Oscillator

Comparator

6 Bit Up /

Down

Counter

1 kHz

LDO1, LDO2

Buck1

Buck2

Buck3

NRST

down

LP3913

SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

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Standby

When the LP3913 is in Standby Mode, the chip is waiting for a valid power-on event to transition to Active Mode.

There are 3 valid wakeup signals. First is the ONOFF pin. Second is Wall Adapter Insertion. Third is the USB

insertion. VBATT must be greater than the battery VUVLO in order to stay in Standby Mode, otherwise the chip

transitions to Power Off Mode. Standby Mode is skipped when advancing from Power Off Mode when a battery

is inserted that is above the battery low alarm threshold.

If the battery is below the battery low alarm threshold, Power Off Mode transitions to Standby Mode. However,

hot insertion of the battery with the adapter connected is NOT permitted. In Standby Mode, the current

consumption is reduced to IQ (10 µA TYP).

Active Mode

All LP3913 circuits are fully operational in Active mode.

Power On/Off Sequencing

Each DC/DC converter (Buck1, Buck2, Buck3, LDO1, LDO2) and the NRST pin of the LP3913 has its own delay

after which it is enabled following a power-on event or disabled following a power-off event. Following the

deglitching of the power-on event, the system bandgaps are enabled. Following this is a 5 ms delay that internal

circuitry requires to cleanly power up. The programmable delays are measured from this time point. Following the

deglitching of a power-down event (up to 5 ms if POWERACK pin is used), the power-down sequencer will start.

Each delay ranges from 0 ms to 63 ms in steps of 1 ms and is factory programmed to the desired values

submitted by the system designer. As illustrated below, the power-on/off sequencing is designed around a 6-bit

up/down timer that is clocked at 1 kHz. A power-on or power-off event will trigger the timer, which counts up from

0 during a power-on sequence and counts down from 5'b11111 during a power-down cycle. The timer output is

connected to 5 comparators with factory programmed timeout values that correspond to the on and off delays for

each DC/DC converter and the NRST pin. Once the timer has incremented beyond the comparator timeout value

during a power-on cycle, the output of the comparator enables the corresponding DC/DC converter or raises the

NRST pin to a logic high level. Subsequently, once the timer has decremented below the comparator timeout

value during a power-down cycle, the output of the comparator will disable the corresponding DC/DC converter

or will activate the NRST pin to a logic low level.

Figure 55. Power up Sequence:

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