LP3913 datasheet(44/70 Pages) TI1

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LP3913

SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

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ADCC Register (0a)h A/D Converter Control Register

D1–0

Access

r/w

Read Only

r/w

Data

VRANGE

IRANGE

ADC Overflow Data Ready

Start

ADC Enable

ADC source

Conversion

selection

0: 2.6V–3.5V

0: 0 mA–605 mA

0: no overflow

0: no data

0: default

0: Disabled

00: battery voltage

1: 2.6V–4.4V

1: 0 mA–1100 mA

1: overflow

1: data ready

1: start

1: Enabled

01: battery charge

conversion

current

10: ADC1

11: ADC2

Reset

ADCD Register (0b)h A/D Converter Output Data Register

Charge current 0A to 1.1A mirrored to 0 µA to 250 µA, ADC measures voltage drop across RSENSE 4.64 kΩ.

D7–0

Access

Read Only 0

Data

Battery voltage:

8’h00 = 2.6V

8’hFF = 3.5V

1 LSB = 0.9 / 256 = (3.5

mV) range 0

8’h00= 2.6V

8’hFF = 4.4V

1 LSB = 1.8 / 256 = (7.0

mV) range 1

Battery charge current 8’h00 = 0

8’hFF = 0.6463V = 605 mA

range 0

8’h00 = 0

8’hFF = 1.175V = 1100 mA

range 1

ADC1:

8’h00 = VREFH = 1.225V

8’hFF = 2*VREFH = 2.45 V

(1 LSB = VREFH/256)

ADC2:

8’h00 = VREFH = 1.225V

8’hFF = 2*VREFH = 2.45 V

(1 LSB = VREFH/256)

Reset

8’h00

The ADC is by default disabled to minimize current consumption and needs to be enabled by setting D2 in the

ADCC register. Writing a logic 1 to bit D3 in the ADC will initiate a conversion. It is advised to select the correct

ADC source before a conversion is started. The A/D converter will set bit D4 in the ADCC register upon the

completion of a conversion, which is typically 4 ms after the start of the conversion. At the same time an interrupt

request will be generated. (See IRQ Register (0d)h Interrupt Request Register).

To save power, disable the ADC by setting bit 2 of D2 to 0. To make repetitive starts, set bit D3 to 0 then to 1 for

processor is the most efficient way to acquire data from successive measurements:

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