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TDA8029HL/C2 датащи(PDF) 30 Page - NXP Semiconductors

номер детали TDA8029HL/C2
подробное описание детали  Low power single card reader
PDF  58 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA8029HL/C2 датащи(HTML) 30 Page - NXP Semiconductors

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2003 Oct 30
30
Philips Semiconductors
Product specification
Low power single card reader
TDA8029
8.10.1.4
Time-Out Configuration register (TOC)
The time-out counter is very useful for processing the clock counting during ATR, the Work Waiting Time (WWT) or the
waiting times defined in protocol T = 1. It should be noted that the 200 and nmax clock counter (nmax = 384 for
TDA8029HL/C1 and nmax = 368 for TDA8029HL/C2) used during ATR is done by hardware when the start session is set.
Specific hardware controls the functionality of BGT in T = 1 and T = 0 protocols and a specific register is available for
processing the extra guard time.
Writing to register TOC is not allowed as long as the card is not activated with a running clock.
Before restarting the 16-bit counter (counters 3 and 2) by writing 61h, 65h, 71h, 75h, F1h or F5h in the TOC register, or
the 24-bit counter (counters 3, 2 and 1) by writing 68h or 7C in the TOC register, it is mandatory to stop them by writing
00h in the TOC register.
Detailed examples of how to use these specific timers can be found in application note
“AN01010”.
The time-out configuration register is used for setting different configurations of the time-out counter as given in Table 43,
all other configurations are undefined.
Table 42 Time-out configuration register, address 8h, read and write
Table 43 Time-out counter configurations
BIT
7
6
543210
Symbol
TOC7
TOC6
TOC5
TOC4
TOC3
TOC2
TOC1
TOC0
Reset value
0
0
0
00000
TOC [7:0]
(HEX)
OPERATING MODE
00
All counters are stopped.
05
Counters 2 and 3 are stopped; counter 1 continues to operate in auto-reload mode.
61
Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value stored in registers
TOR3 and TOR2 is started after 61h is written in register TOC. When the terminal count is reached, an
interrupt is given, and bit TO3 in register USR is set. The counter is stopped by writing 00h in register
TOC, and should be stopped before reloading new values in registers TOR2 and TOR3.
65
Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter. Counter 1 starts
counting the content of register TOR1 on the first start-bit (reception or transmission) detected on pin I/O
after 65h is written in register TOC. When counter 1 reaches its terminal count, an interrupt is given, bit
TO1 in register USR is set and the counter automatically restarts the same count until it is stopped. It is
not allowed to change the content of register TOR1 during a count. Counters 3 and 2 are wired as a
single 16-bit counter and start counting the value in registers TOR3 and TOR2 when 65h is written in
register TOC. When the counter reaches its terminal count, an interrupt is given and bit TO3 is set within
register USR. Both counters are stopped when 00h is written in register TOC. Counters 3 and 2 shall be
stopped by writing 05h in register TOC before reloading new values in registers TOR2 and TOR3.
68
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in registers TOR3,
TOR2 and TOR1 is started after 68h is written in register TOC. The counter is stopped by writing 00h in
register TOC. It is not allowed to change the content of registers TOR3, TOR2 and TOR1 within a count.
71
Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. After writing this value, counting the
value stored in registers TOR3 and TOR2 is started on the first start-bit detected on pin I/O (reception or
transmission) and then on each subsequent start-bit. It is possible to change the content of registers
TOR3 and TOR2 during a count, the current count will not be affected and the new count value will be
taken into account at the next start-bit. The counter is stopped by writing 00h in register TOC. In this
configuration, registers TOR3, TOR2 and TOR1 must not be all zero.



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