TDA8029HLSLASHC2 datasheet(19/58 Pages) PHILIPS

19 / 58 page

2003 Oct 30

Philips Semiconductors

Product speciﬁcation

Low power single card reader

TDA8029

Table 13 Description of register bits

Table 14 Enhanced UART modes

BIT

SYMBOL

DESCRIPTION

SM0/FE

The function of this bit is determined by SMOD0, bit 6 of register PCON. If SMOD0 is set

then this bit functions as FE. This bit functions as SM0 when SMOD0 is reset. When

used as FE, this bit can only be cleared by software.

SM0: Serial port mode bit 0. See Table 14.

FE: Framing Error bit. This bit is set by the receiver when an invalid stop bit is

detected; see Fig.6. The FE bit is not cleared by valid frames but should be cleared by

software. The SMOD0 bit in register PCON must be set to enable access to FE.

SM1

Serial port mode bit 1. See Table 14.

SM2

Serial port mode bit 2. Enables the automatic address recognition feature in modes

2 or 3. If SM2 = 1, bit Rl will not be set unless the received 9th data bit (RB8) is logic 1;

indicating an address and the received byte is a given or broadcast address. In mode 1,

if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the

received byte is a given or broadcast address. In mode 0, SM2 should be logic 0.

REN

Enables serial reception. Set by software to enable reception. Cleared by software to

disable reception.

TB8

The 9th data bit transmitted in modes 2 and 3. Set or cleared by software as desired.

In mode 0, TB8 is not used.

RB8

The 9th data bit received in modes 2 and 3. In mode 1, if SM2 = 0, RB8 is the stop bit

that was received. In mode 0, RB8 is not used.

1Tl

Transmit interrupt ﬂag. Set by hardware at the end of the 8th bit time in mode 0, or at

the beginning of the stop bit in the other modes, in any serial transmission. Must be

cleared by software.

0Rl

Receive interrupt ﬂag. Set by hardware at the end of the 8th bit time in mode 0, or

halfway through the stop bit time in the other modes, in any serial reception (except if

SM2 = 1, as described for SM2). Must be cleared by software.

SM0

SM1

MODE

DESCRIPTION

BAUD RATE

shift register

1/12fXTAL1

8-bit UART

variable

9-bit UART

1/32 or 1/64fXTAL1

9-bit UART

variable

8.3.2

AUTOMATIC ADDRESS RECOGNITION

Automatic address recognition is a feature which allows

the UART to recognize certain addresses in the serial bit

stream by using hardware to make the comparisons. This

feature saves a great deal of software overhead by

eliminating the need for the software to examine every

serial address which passes by the serial port. This feature

is enabled by setting the SM2 bit in register SCON. In the

9-bit UART modes (modes 2 and 3), the Receive Interrupt

flag (RI) will be automatically set when the received byte

contains either the ‘given’ address or the ‘broadcast’

address. The 9-bit mode requires that the 9th information

bit is a logic 1 to indicate that the received information is an

address and not data. Figure 7 gives a summary.

The 8-bit mode is called mode 1. In this mode the RI flag

will be set if SM2 is enabled and the information received

has a valid stop bit following the 8 address bits and the

information is either a given or a broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the automatic address recognition feature allows a

master to selectively communicate with one or more

slaves by invoking the given slave address or addresses.

All of the slaves may be contacted by using the broadcast

TDA8029HL/C2 датащи(PDF) 19 Page - NXP Semiconductors

TDA8029HL/C2 датащи(HTML) 19 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

датащи скачать

ссылки URL