TDA8029HLSLASHC2 datasheet(45/58 Pages) PHILIPS

45 / 58 page

2003 Oct 30

Philips Semiconductors

Product speciﬁcation

Low power single card reader

TDA8029

When in Power-down or Sleep mode, card extraction or

insertion, overcurrent on VCC, or HIGH level on pins RST

or RESET will wake up the chip.

The same occurs in case of a falling edge on RX if bit

ENRX is set, or on INT1_N if bit ENINT1 is set and if

INT1_N is enabled within the controller.

If only INT1_N should wake up the TDA8029, then INT1_N

must be enabled in the controller, and ENINT1 only should

be set.

If RX should wake up the TDA8029, then INT1_N must be

enabled in the controller, and ENRX and ENINT1 should

be set.

In case of wake up by RX, then the first received

characters may be lost, depending on the baud rate on the

serial link. (The controller waits for 1536 clock cycles

before leaving Power-down mode).

For more details about the use of these modes, please

refer to the application notes

“AN00069” and “AN01005”.

8.16

Activation sequence

When the card is inactive, VCC, CLK, RST and I/O are

LOW, with low impedance with respect to GNDC. The

DC/DC converter is stopped.

When everything is satisfactory (voltage supply, card

present and no hardware problems), the system controller

may initiate an activation sequence of the card. Figure 12

shows the activation sequence.

After leaving the UART reset mode, and then configuring

the necessary parameters for the UART, it may set the bit

START in register PCR (t0). The following sequence will

take place:

• The DC/DC converter is started (t1)

• VCC starts rising from 0 to 5 V or 3 V with a controlled

rise time of 0.17 V/

µs typically (t2)

• I/O rises to VCC (t3), (Integrated 14 kΩ pull-up to VCC)

• CLK is sent to the card and RST is enabled (t4).

After a number of clock pulses that can be counted with the

time out counter, bit RSTIN may be set by software, then

pin RST rises to VCC.

The sequencer is clocked by 1/64fint which leads to a time

interval T of 25

µs typical. Thus t1 =0to 3/64T,

t2 =t1 + 3/2T, t3 =t1 + 7/2T, and t4 =t1 + 4T.

handbook, full pagewidth

START

VUP

VCC

I/O

RSTIN

CLK

RST

t4 = tact

ATR

FCE684

Fig.12 Activation sequence.

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