TDA8029HLSLASHC2 datasheet(25/58 Pages) PHILIPS

25 / 58 page

2003 Oct 30

Philips Semiconductors

Product speciﬁcation

Low power single card reader

TDA8029

8.6

Expanded data RAM addressing

The TDA8029 has internal data memory that is mapped

into four separate segments.

The four segments, shown in Fig.9, are:

1. The lower 128 bytes of RAM (addresses 00h to 7Fh),

which are directly and indirectly addressable.

2. The upper 128 bytes of RAM (addresses 80h to FFh),

which are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses

80h to FFh), which are directly addressable only.

4. The 512 bytes expanded RAM (XRAM 00h to 1FFh)

are indirectly accessed by move external instructions,

MOVX, if the EXTRAM bit (bit 1 of register AUXR) is

cleared.

The lower 128 bytes can be accessed by either direct or

indirect addressing. The upper 128 bytes can be accessed

by indirect addressing only. The upper 128 bytes occupy

the same address space as the SFRs. That means they

have the same address, but are physically separate from

SFR space.

When an instruction accesses an internal location above

address 7Fh, the CPU knows whether the access is to the

upper 128 bytes of data RAM or to the SFR space by the

addressing mode used in the instruction. Instructions that

use direct addressing access SFR space. For example:

MOV A0h, #data accesses the SFR at location 0A0h

(which is register P2).

Instructions that use indirect addressing access the upper

128 bytes of data RAM. For example: MOV @R0, #data

where R0 contains 0A0h, accesses the data byte at

address 0A0h, rather than P2 (whose address is 0A0h).

The XRAM can be accessed by indirect addressing, with

EXTRAM bit (register AUXR bit 1) cleared and MOVX

instructions. This part of memory is physically located

on-chip, logically occupies the first 512 bytes of external

data memory.

When EXTRAM = 0, the XRAM is indirectly addressed,

using the MOVX instruction in combination with any of the

registers R0, R1 of the selected bank or DPTR. An access

to XRAM will not affect ports P0, P3.6 (WR) and P3.7 (RD).

P2 is output during external addressing. For example:

MOVX @R0, A where R0 contains 0A0h, access the

EXTRAM at address 0A0h rather than external memory.

An access to external data memory locations higher than

1FFh (i.e., 0200h to FFFFh) will be performed with the

MOVX DPTR instructions in the same way as in the

standard 80C51, so with P0 and P2 as data/address bus,

and P3.6 and P3.7 as write and read timing signals.

When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will

be similar to the standard 80C51. MOVX @Ri will provide

an 8-bit address multiplexed with data on port 0 and any

output port pins can be used to output higher order

address bits. This is to provide the external paging

capability. MOVX @DPTR will generate a 16-bit address.

Port 2 outputs the high order eight address bits (the

contents of DPH) while port 0 multiplexes the low-order

eight address bits (DPL) with data. MOVX @Ri and

MOVX @DPTR will generate either read or write signals

on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the

256 bytes RAM (lower and upper RAM) internal data

memory. The stack must not be located in the XRAM.

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