TDA8029HLSLASHC2 datasheet(22/58 Pages) PHILIPS

22 / 58 page

2003 Oct 30

Philips Semiconductors

Product speciﬁcation

Low power single card reader

TDA8029

8.4

Interrupt priority structure

The TDA8029 has a 6-source 4-level interrupt structure.

There are three SFRs associated with the 4-level interrupt: IE, IP and IPH. The Interrupt Priority High (IPH) register

implements the 4-level interrupt structure. The IPH is located at SFR address B7h.

The function of the IPH is simple and when combined with the IP determines the priority of each interrupt. The priority of

each interrupt is determined as shown in Table 20.

Table 20 Priority bits

Table 21 Interrupt table

Notes

1. Level activated.

2. Transition activated.

8.4.1

INTERRUPT ENABLE (IE) REGISTER

Table 22 Interrupt enable register bits

Table 23 Description of register bits

IPH BIT n

IP BIT n

INTERRUPT PRIORITY LEVEL

level 0 (lowest priority)

level 1

level 2

level 3 (highest priority)

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR

VECTOR ADDRESS

(HEX)

IE0

N(1); Y(2)

TF0

IE1

N(1); Y(2)

TF1

RI, TI

TF2, EXF2

BIT

543210

Symbol

−

ET2

ET1

EX1

ET0

EX0

BIT

SYMBOL

DESCRIPTION(1)

7EA

Global disable. If EA = 0, all interrupts are disabled; If EA = 1, each interrupt can be

individually enabled or disabled by setting or clearing its enable bit.

−

Not implemented. Reserved for future use; note 2.

ET2

Timer 2 interrupt enable. ET2 = 1 enables the interrupt; ET2 = 0 disables the interrupt.

4ES

Serial port interrupt enable. ES = 1 enables the interrupt; ES = 0 disables the interrupt.

ET1

Timer 1 interrupt enable. ET1 = 1 enables the interrupt; ET1 = 0 disables the interrupt.

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