TDA8029HLSLASHC2 datasheet(27/58 Pages) PHILIPS

27 / 58 page

2003 Oct 30

Philips Semiconductors

Product speciﬁcation

Low power single card reader

TDA8029

8.8

Mask ROM devices

When none of the security bits SB1 and SB2 are

programmed, the code in the program memory can be

verified. If the encryption table is programmed, the code

will be encrypted when verified. When only security bit 1 is

programmed, MOVC instructions executed from external

program memory are disabled from fetching code bytes

from the internal memory. When security bits SB1 and SB2

are programmed, in addition to the above, verify mode is

disabled.

The 64 bytes of the encryption array are initially not

programmed (all logic 1s).

Table 31 Program security bits for TDA8029

Note

1. Any other combination of the security bits is not

defined.

8.9

ROM code submission for 16 kbytes ROM

device TDA8029

When submitting ROM code for 16 kbytes ROM devices,

the following must be specified:

• 16 kbyte user ROM data

• 64 byte ROM encryption key

• ROM security bits.

8.10

Smart card reader control registers

The TDA8029 has one analog interface for five contacts

cards. The data to or from the card are fed into an ISO

UART.

The Card Select Register (CSR) contains a bit for resetting

the ISO UART (logic 0 = active). This bit is reset after

power-on, and must be set to logic 1 before starting any

operation. It may be reset by software when necessary.

Dedicated registers allow to set the parameters of the ISO

UART:

• Programmable Divider Register (PDR)

• Guard Time Register (GTR)

• UART Control Registers (UCR1 and UCR2)

• Clock Configuration Register (CCR).

The parameters of the ETU counters are set by:

• Time-Out Configuration register (TOC)

• Time-Out Registers (TOR1, TOR2 and TOR3).

The Power Control Register (PCR) is a dedicated register

for controlling the power to the card.

When the specific parameters of the card have been

programmed, the UART may be used with the following

registers:

• UART Receive and Transmit Registers (URR and UTR)

• UART Status Register (USR)

• Mixed Status Register (MSR).

In reception mode, a FIFO of 1 to 8 characters may be

used, and is configured with the FIFO Control Register

(FCR). This register is also used for the automatic

retransmission of NAKed characters in transmission

mode.

The Hardware Status Register (HSR) gives the status of

the supply voltage, the hardware protections, the SDWN

request and the card movements.

USR and HSR give interrupts on INT0_N when some of

their bits have been changed.

MSR does not give interrupts, and may be used in polling

mode for some operations. For this use, the bit TBE/RBF

within USR may be masked.

A 24-bit time-out counter may be started for giving an

interrupt after a number of ETU programmed in registers

TOR1, TOR2 and TOR3. It will help the controller for

processing different real time tasks (ATR, WWT, BWT,

etc.) mainly if controllers and card clock are asynchronous.

This counter is configured with register TOC, that may be

used as a 24-bit or as a 16-bit + 8-bit counter. Each

counter may be set for starting to count once data written,

on detection of a start bit on I/O, or as auto-reload.

LOCK BIT

PROGRAMMED(1)

PROTECTION DESCRIPTION

SB1

SB2

no program security features

enabled. If the encryption array is

programmed, code verify will be

encrypted.

yes

MOVC instructions executed from

external program memory are

disabled from fetching code bytes

from internal memory

yes

same as above, also verify is

disabled

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