RM0319 datasheet(337/368 Pages) STMICROELECTRONICS

337 / 368 page

RM0319

Power, reset and clock control

Doc ID 022640 Rev 3

337/368

30.5.8

Clock synthesizer

The clock synthesizer is a digital signal generator. It is used to perform a fractional clock

divider.

Note:

Refer to “Auxiliary clock synthesizer register bit assignments” table in RM0321: SPEAr320S

address map and registers, for the register fields mentioned in this section.

Giving an input clock with frequency Fin and two integers X (synt_xdiv field of programming

⎟

⎠

⎞

⎜

⎝

⎛

∗

Fin

out

with X<Y/2 if the post divider is enabled (synt_clkout_sel field is cleared); while:

⎟

⎠

⎞

⎜

⎝

⎛

∗

Fin

out 2

with X <Y/2, if post divider is disabled (synt_clkout_sel field is set).

The clock synthesizer is based on Y-modulo counter incremented by X. After reset the

counter value is zero and it increments of X every input clock cycle. If N is the number of

input clock cycle the output is high when:

≥

∗

The counter loads the value Y-NX a clock cycle after that it is verified the previous condition,

the output become low and the process iterates again. If Y is a multiple of X

is a constant and the output period is

out

∗

The output frequency is given by the Fout formula above.

When Y/X is not an integer value, the output period swings between N and N+1 times the

input clock period, with N the integer part of Y/X.

This means that the maximum period drift is of one input clock period.

For example:

With Fout= 40 MHz, Fin= 333 MHz the synthesizer parameters are:

X=40 and Y=333

This means that the output clock period is on average: Tout = 8.325 * Tin.

The output period will be 8 or 9 times the input clock period:

Tout = 8 * 3 = 24 ns and Tout = 9 * 3 = 27 ns

The maximum output period drift is 27-24 =3 ns.

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