RM0319 datasheet(332/368 Pages) STMICROELECTRONICS

332 / 368 page

Power, reset and clock control

RM0319

332/368

Doc ID 022640 Rev 3

30.5.2

PLL programming

The system clocks are generated by three PLLs:

●

PLL1: fully programmable; it generates the clock for the CPU and AMBA system.

●

PLL2: fully programmable; it generates the clock for the RAS block and the DDR

multiport controller (MPMC).

Both PLL1 and PLL2 offer an EMI reduction mode (dithering mode) than can replace all

traditional drop methods for electro-magnetic interference.

●

PLL3: it generates the clock for USB controllers. Unlike PLL2 and PLL2, PLL3 is not

programmable.

PLL clock source selection

The clock sources for the PLLs are:

●

PLL1: 24 MHz oscillator or PL_CLK4 pin

●

PLL2: 24 MHz oscillator or PL_CLK3 pin

The clock sources for PLL1 and PLL2 can be selected by software. At reset the 24 MHz

source is selected.

●

PLL3: 24 MHz oscillator. Since PLL3 is not programmable, if the USB functionality is

required in the application, then the external oscillator frequency must be 24 MHz.

PLL operating modes (normal, dithered, fractional-N synthesis)

PLL1 and PLL2 can work in three operating modes:

●

Normal mode (Dither-off mode): the PLL behaves as a normal PLL.

●

Fractional-N synthesis mode: with this mode it is possible to select VCO frequencies

that are not integer multiples of the reference frequency.

●

Dither-on mode:

–

Double side modulation: a triangular wave is added to the VCO frequency.

–

Single side modulation: similar to double side modulation, with the difference that

the modulation is only subtracting from the main frequency.

To reduce the electromagnetic emission both PLL1 and PLL2 can be programmed to work in

dithered mode.

When the dithered mode is enabled, the PLL output clock is modulated and the frequency

assumes a triangular shape. In this way the clock power spectrum is spread on a small

range (programmable) of frequencies decreasing the emission power peak.

This method replaces the other traditional methods of EMI reduction, as filtering, ferrite

beads, chokes, adding power layers and ground planes to PCBs, metal shielding, allowing

sensible cost saving for customers.

30.5.3

Clock distribution scheme

Core clock control

To enable the software to control the relative frequency of the core clock (SYS_CLK) and the

bus clock (HCLK), the software can program the HCLKDivSel bits in the SCCTRL register).

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