RM0319 datasheet(252/368 Pages) STMICROELECTRONICS

252 / 368 page

Fast infrared port (IRDA)

RM0319

252/368

Doc ID 022640 Rev 3

These signals can either be used as either interrupt requests (Section 19.4) or DMA

requests, and they are reset on the occurrence of the request clear signal (REQCLR) which

is either set by software via IrDA_ICR register or generated by a DMA controller,

respectively. The burst size is programmable by the field BS of IrDA_CONF register.

Transmission state

In order to start to transmit data, the software writes the frame size to the 12 bit field TFS of

transmission frame size register (IrDA_TFS). Then, the FIrDA controller changes to the

transmission state and the FIFO unit asserts burst requests (BREQ_INT) until the amount of

data to be transferred is equal or less than BS.

If the remaining data is equal to BS, a last burst request is issued using LBREQ_INT,

otherwise single requests are issued using SREQ_INT until the last data item is ready, when

LSREQ_INT is used.

Note:

The size of the frame to be transmitted is not necessarily a multiple of 4, so the last word

could be filled up with dummy bytes. The hardware transmits only the valid bytes of the last

word by means of the bit field TFS of IrDA_TFS register.

The data is buffered in an 8-stage 32 bit shift register before it is processed by the FIrDA

controller. If a FIFO underflow occurs before all bytes of a frame has been shifted into the

FIFO, a frame invalid interrupt (FI_INT, Section 19.3.6) is generated, the transmission is

aborted and all pending bytes in the peripheral are discarded.

The next frame to be transmitted can be copied into the buffer only when all bytes of the

current frame are completely transferred to the wrapper unit. The software can write the size

of the next frame into TFS immediately after the last word of the current frame has been

written to the IrDA_TXB register.

Reception state

The received bytes of the frame are shifted from the wrapper unit to the FIFO where the

data is buffered. The received bytes are counted by a 12 bit counter and that value can be

read by software in the received frame size register (IrDA_RFS). If this number is greater

than the maximum number of received bytes (MNRB field in the IrDA_PARA register) the

currently received frame becomes invalid, a buffer overflow occurs and a frame invalid

interrupt (FI_INT, Section 19.4) is generated.

The signal frame complete indicates that the whole data of the current received frame has

been moved to the buffer. The bytes of this frame have to be moved out of the buffer by

software before the next received frame will be shifted into the buffer, if not the next received

frame will be completely discarded.

The buffered data is moved out at full speed bus using DMA burst transfers: the FIFO unit

asserts burst requests (BREQ_INT) until the amount of data to be transferred is equal or

less than BS. If the remaining data is equal to BS, a last burst request is issued using

LBREQ_INT, otherwise single requests are issued using SREQ_INT until the last data item

is ready, when a LSREQ_INT is used.

Note:

The size of the frame to be received is not necessarily a multiple of 4, so the upper bytes of

the last word could be invalid. The SW has to check for invalid bytes of the last word by

means of the bit field RFS of the IrDA_RFS register.

Along with the IrLAP bytes, the CRC bytes are also transferred to the memory. The CRC

bytes can be double-checked by the software for the purpose of testing.

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