RM0319 datasheet(106/368 Pages) STMICROELECTRONICS

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External memory interface (EMI)

RM0319

106/368

Doc ID 022640 Rev 3

Figure 26.

EMI read cycle

Note:

EMI_WAIT# can be used to increase the cycle time (slow peripherals).

9.3.2

Data flow

The data transfer protocol will be based on the timing diagrams shown in EMI cycle

definition. Prior to any read/write operation, the timing and control registers should be

programmed. The timing registers will be used to time the EMI-interface signals in respect to

the HCLK cycles. There are different registers for EMI-interface signals for extending them

to a specified number of HCLK cycles. The Control register provides information about the

peripheral connected.

If a write operation is desired on the peripheral, then an AHB write operation is initiated.

Similarly, for a read operation AHB read is done. The EMI supports 8 bit and 16 bit

peripherals. The following table lists the transactions supported by EMI:

For transactions not supported, AHB Error is generated on the bus and an interrupt is

raised. Interrupt can be checked in the IRQ register.

The data phase (i.e. the data bus along with the control signals) will be extended until the

EMI_WAIT# is asserted low by the external peripheral. If this feature is not used, as

mentioned in the Ack_reg, this signal is ignored.

Following timing diagrams details the timing and flow of different signals and also indicates

which registers corresponds to what timings.

READ DATA

BE#[3:0]

ADDR[28:0]

EMI_ADB

EMI_ADDLE

EMI_CE#

EMI_OE#

EMI_WAIT#

Table 35.

EMI data flow

Peripheral Connected

AHB Access

Support

16 bit

32 bit

No (AHB Error, Interrupt)

16 bit

Yes

16 bit

8 bit

Yes

8 bit

32 bit

No (AHB Error, Interrupt)

8 bit

16 bit

No (AHB Error, Interrupt)

8 bit

Yes

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