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PM0056 датащи(PDF) 155 Page - STMicroelectronics |
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PM0056 датащи(HTML) 155 Page - STMicroelectronics |
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155 / 156 page ![]() DocID15491 Rev 5 155/156 PM0056 Revision history 5 Revision history Table 50. Document revision history Date Revision Changes 03-Apr-2009 1 Initial release. 26-Oct-2009 2 Table 45: Priority grouping modified. 16-Apr-2010 3 Modified Table 14: Peripheral memory bit-banding regions on page 28 (peripheral bit-band alias and peripheral bit-band region swapped) Added Section 4.2: Memory protection unit (MPU) on page 105. Modified Table 44: NVIC register map and reset values on page 128 supporting up to 81 interrupts 28-Feb-2011 4 Added reference to STM32F20xxx, STM32F21xxx and STM32L1xx products in title and fisrt page. Modified NVIC_ISPR0 register base moved to offset 0x100 in Table 44: NVIC register map and reset values on page 128 . To support STM32L anf STM32F2 series based on r2p0 core: Added SCB_ACTLR register, modified SCB_CPUID and SCB_CCR registers . 27-May-2013 5 Modified bit numbers in register description for Section 4.4.4: Vector table offset register (SCB_VTOR). Modified STK_CTRL reset value in Section 4.5.1: SysTick control and status register (STK_CTRL). |
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