PM0056 datasheet(148/156 Pages) STMICROELECTRONICS

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Core peripherals

PM0056

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DocID15491 Rev 5

4.4.14

System control block design hints and tips

Ensure software uses aligned accesses of the correct size to access the system control

block registers:

•

except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses

•

for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word

accesses.

The processor does not support unaligned accesses to system control block registers.

In a fault handler. to determine the true faulting address:

Read and save the MMFAR or BFAR value.

Read the MMARVALID bit in the MMFSR, or the BFARVALID bit in the BFSR. The

MMFAR or BFAR address is valid only if this bit is 1.

Software must follow this sequence because another higher priority exception might change

the MMFAR or BFAR value. For example, if a higher priority handler preempts the current

fault handler, the other fault might change the MMFAR or BFAR value.

4.4.15

SCB register map

The table provides shows the System control block register map and reset values.

The base address of the SCB register block is 0xE000 ED00 for register described in

Table 48.

For STM32L and STM32F2, an auxiliary control register is added with base address of the

SCB register block set to 0xE000 E008, see Table 47.

Table 47. SCB register map and reset value for STM32F2 and STM32L

Offset

0x00

SCB_ACTLR

Implementer

Variant

Constant

PartNo

Revision

Reset Value

0000000 0000000000 00 00 0 0 0 0 0 0 0 0 0 0 0

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