AM79C972BVCW datasheet(118/130 Pages) AMD

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118

Am79C972

H_RESET and is not affected by

S_RESET or setting the STOP bit

MAPINT

MII Management Auto-Poll Inter-

rupt. The MII Auto-Poll interrupt is

set by the Am79C972 controller

to indicate that the currently read

status does not match the stored

status

indicating

change in state for the external

PHY. A change in the Auto-Poll

Access Method (BCR32, Bit 11)

will reset the shadow register and

will not cause an interrupt on the

first access from the Auto-Poll

section. Subsequent accesses

will generate an interrupt if the

shadow register and the read

When MAPINT is set to 1, INTA is

asserted if the enable bit MAP-

INTE is set to 1.

Read/Write accessible always.

MAPINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MAPINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MAPINTE

MII Auto-Poll Interrupt Enable. If

MAPINTE is set, the MAPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

MAPINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP bit

MCCINT

MII

Management

Command

Complete Interrupt. The MII Man-

agement Command Complete In-

terrupt is set by the Am79C972

controller when a read or write

operation to the MII Data Port

(BCR34) is complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MCCINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCINTE

MII

Management

Command

Complete Interrupt Enable. If

MCCINTE is set to 1, the MC-

CINT bit will be able to set the

INTR bit when the host reads or

writes to the MII Data Port

(BCR34) only. Internal MII Man-

agement Commands will not gen-

erate an interrupt. For instance

Auto-Poll state machine generat-

ed MII management frames will

not generate an interrupt upon

completion unless there is a com-

pare error which get reported

through the MAPINT (CSR7, bit

6) interrupt or the MCCIINTE is

set to 1.

Read/Write accessible always.

MCCINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCIINT

MII

Management

Command

Complete Internal Interrupt. The

MII

Management

Command

Complete Interrupt is set by the

Am79C972 controller when a

read or write operation on the MII

management port is complete

from an internal operation. Exam-

ples of internal operations are

Auto-Poll or MII Management

Port generated MII management

frames. These are normally hid-

den to the host.

When MCCIINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCIINT is cleared by the host

by writing a 1. Writing a 0 has no

effect. MCCIINT is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCIINTE

MII

Management

Command

Complete Internal Interrupt En-

able. If MCCIINTE is set to 1, the

MCCIINT bit will be able to set

the INTR bit when the internal

state

machines

generate

MII

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