AM79C972BVCW datasheet(31/130 Pages) AMD

31 / 130 page

Am79C972

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55H (byte 0) and AAH (byte 1).

Slave Cycle Termination

There are three scenarios besides normal completion

of a transaction where the Am79C972 controller is the

target of a slave cycle and it will terminate the access.

Disconnect When Busy

The Am79C972 controller cannot service any slave ac-

cess while it is reading the contents of the EEPROM.

Simultaneous access is not allowed in order to avoid

conflicts, since the EEPROM is used to initialize some

of the PCI configuration space locations and most of

the BCRs and CSR116. The EEPROM read operation

will always happen automatically after the deassertion

of the RST pin. In addition, the host can start the read

operation by setting the PREAD bit (BCR19, bit 14).

While the EEPROM read is on-going, the Am79C972

controller will disconnect any slave access where it is

the target by asserting STOP together with DEVSEL,

while driving TRDY high. STOP will stay asserted until

the end of the cycle.

Note that I/O and memory slave accesses will only be

disconnected if they are enabled by setting the IOEN or

MEMEN bit in the PCI Command register. Without the

enable bit set, the cycles will not be claimed at all.

Since H_RESET clears the IOEN and MEMEN bits for

the automatic EEPROM read after H_RESET, the dis-

connect only applies to configuration cycles.

A second situation where the Am79C972 controller will

generate a PCI disconnect/retry cycle is when the host

tries to access any of the I/O resources right after hav-

ing read the Reset register. Since the access gener-

ates an internal reset pulse of about 1

µs in length, all

further slave accesses will be deferred until the internal

reset operation is completed. See Figure 6.

Disconnect Of Burst Transfer

The Am79C972 controller does not support burst ac-

cess to the configuration space, the I/O resources, or to

the Expansion Bus. The host indicates a burst transac-

tion by keeping FRAME asserted during the data

phase. When the Am79C972 controller sees FRAME

and IRDY asserted in the clock cycle before it wants to

assert TRDY, it also asserts STOP at the same time.

The transfer of the first data phase is still successful,

since IRDY and TRDY are both asserted. See Figure 7.

Figure 6.

Disconnect Of Slave Cycle When Busy

Figure 7.

Disconnect Of Slave Burst Transfer - No

Host Wait States

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

CMD

PAR

DATA

ADDR

21485C-9

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

PAR

DATA

1st DATA

21485C-10

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