AM79C972BVCW datasheet(114/130 Pages) AMD

114 / 130 page

114

Am79C972

Read/Write accessible always.

LTINTEN

cleared

H_RESET or S_RESET and is

unaffected by STOP.

13-12

RES

Reserved locations. Written as

zeros and read as undefined.

SINT

System Interrupt is set by the

Am79C972 controller when it de-

tects a system error during a bus

master transfer on the PCI bus.

System errors are data parity er-

ror, master abort, or a target

abort. The setting of SINT due to

data parity error is not dependent

on the setting of PERREN (PCI

Command register, bit 6).

When SINT is set, INTA is assert-

ed if the enable bit SINTE is 1.

Note that the assertion of an in-

terrupt due to SINT is not depen-

dent on the state of the INEA bit,

since INEA is cleared by the

STOP reset generated by the

system error.

Read/Write accessible always.

SINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. The state of SINT is not af-

fected by clearing any of the PCI

Status register bits that get set

when

data

parity

error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13), or target

abort (RTABORT, bit 12) occurs.

SINT is cleared by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

SINTE

System Interrupt Enable. If SIN-

TE is set, the SINT bit will be able

to set the INTR bit.

Read/Write accessible always.

SINTE is set to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

9-8

RES

Reserved locations. Written as

zeros and read as undefined.

EXDINT

Excessive Deferral Interrupt is

set by the Am79C972 controller

when the transmitter has experi-

enced Excessive Deferral on a

transmit frame, where Excessive

Deferral is defined in the ISO

8802-3 (IEEE/ANSI 802.3) stan-

dard.

When EXDINT is set, INTA is as-

serted if the enable bit EXDINTE

is 1.

Read/Write accessible always.

EXDINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

EXDINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

EXDINTE

Excessive Deferral Interrupt En-

able. If EXDINTE is set, the

EXDINT bit will be able to set the

INTR bit.

Read/Write accessible always.

EXDINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MPPLBA

Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

at its default value of 0, the

Am79C972 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If

MPPLBA is set to 1, the destina-

tion address of the Magic Packet

frame can be unicast, multicast,

or broadcast. Note that the set-

ting of MPPLBA only affects the

address detection of the Magic

Packet frame. The Magic Packet

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless

what

kind

destination address it has. This

bit is OR’ed with EMPPLBA bit

(CSR116, bit 6).

Read/Write accessible always.

MPPLBA is set to 0 by H_RESET

or S_RESET and is not affected

by setting the STOP bit.

MPINT

Magic Packet Interrupt. Magic

Packet Interrupt is set by the

Am79C972 controller when the

device is in the Magic Packet

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