AM79C972BVCW datasheet(121/130 Pages) AMD

121 / 130 page

Am79C972

121

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DRCVBC

Disable

Receive

Broadcast.

When

set,

disables

the

Am79C972 controller from re-

ceiving

broadcast

messages.

Used for protocols that do not

support broadcast addressing,

except as a function of multicast.

DRCVBC is cleared by activation

H_RESET

S_RESET

(broadcast messages will be re-

ceived) and is unaffected by

STOP.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DRCVPA

Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the Am79C972 controller

will be disabled. Frames ad-

dressed to the nodes individual

physical address will not be rec-

ognized.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

12-9

RES

Reserved locations. Written as

zeros and read as undefined.

8-7 PORTSEL[1:0] Port Select bits allow for software

controlled selection of the net-

work medium. The only legal val-

ues for this field are 11 and 10.

A value of 11 selects the MII port

and a value of 10 selects the

GPSI port.

Read/Write accessible only when

either the STOP or the SPND bit

is set. Cleared by H_RESET or

S_RESET and is unaffected by

STOP.

INTL

Internal Loopback. See the de-

scription of LOOP (CSR15, bit 2).

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DRTY

Disable Retry. When DRTY is set

to 1, the Am79C972 controller will

attempt only one transmission. In

this mode, the device will not pro-

tect the first 64 bytes of frame

data in the Transmit FIFO from

being overwritten, because auto-

matic retransmission will not be

necessary. When DRTY is set to

0, the Am79C972 controller will

attempt 16 transmissions before

signaling a retry error.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

FCOLL

Force Collision. This bit allows

the collision logic to be tested.

The Am79C972 controller must

be in internal loopback for FCOLL

to be valid. If FCOLL = 1, a colli-

sion will be forced during loop-

back

transmission

attempts,

which will result in a Retry Error.

If FCOLL = 0, the Force Collision

logic will be disabled. FCOLL is

defined

after

the

initialization

block is read.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DXMTFCS

Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. When DXMTFCS is set to

1, no FCS is generated or sent

with

the

transmitted

frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in TMD1.

When APAD_XMT bit (CSR4,

bit11) is set to 1, the setting of

DXMTFCS has no effect on

frames shorter than 64 bytes.

DXMTFCS

set

and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

If ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in TMD1.

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