AM79C972BVCW datasheet(117/130 Pages) AMD

117 / 130 page

Am79C972

117

ed by S_RESET or by setting the

STOP bit.

RDMD

Receive

Demand,

when

set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the receive poll-time counter to

elapse. If RXON is not enabled,

RDMD has no meaning and no

receive Descriptor Ring access

will occur.

RDMD is required to be set if the

RXDPOLL bit in CSR7 is set. Set-

ting RDMD while RXDPOLL = 0

merely hastens the Am79C972

controller’s response to a receive

Descriptor Ring Entry.

Read/Write accessible always.

RDMD is set by writing a 1. Writ-

ing a 0 has no effect. RDMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a re-

ceive

Descriptor.

RDMD

cleared by H_RESET. RDMD is

unaffected by S_RESET or by

setting the STOP bit.

RXDPOLL

Receive Disable Polling. If RXD-

POLL is set, the Buffer Manage-

ment Unit will disable receive

polling. Likewise, if RXDPOLL is

cleared, automatic receive poll-

ing is enabled. If RXDPOLL is

set, RDMD bit in CSR7 must be

set in order to initiate a manual

poll of a receive descriptor. Re-

ceive Descriptor Polling will not

take place if RXON is reset.

Read/Write accessible always.

RXDPOLL

cleared

H_RESET. RXDPOLL is unaf-

fected by S_RESET or by setting

the STOP bit.

STINT

Software Timer Interrupt. The

Software Timer interrupt is set by

the Am79C972 controller when

the Software Timer counts down

to 0. The Software Timer will im-

mediately load the STVAL (BCR

31, bits 5-0) into the Software

Timer and begin counting down.

When STINT is set to 1, INTA is

asserted if the enable bit STINTE

is set to 1.

Read/Write accessible always.

STINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

STINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

STINTE

Software Timer Interrupt Enable.

If STINTE is set, the STINT bit

will be able to set the INTR bit.

Read/Write accessible always.

STINTE is set to 0 by H_RESET

and is not affected by S_RESET

or setting the STOP bit

MREINT

MII Management Read Error In-

terrupt. The MII Read Error inter-

rupt is set by the Am79C972

controller to indicate that the cur-

rently read register from the ex-

ternal

PHY

invalid.

The

contents of BCR34 are incorrect

and that the operation should be

performed again. The indication

of an incorrect read comes from

the PHY. During the read turn-

around time of the MII manage-

ment frame the external PHY

should drive the MDIO pin to a

LOW state. If this does not hap-

pen, it indicates that the PHY and

the Am79C972 controller have

lost synchronization.

When MREINT is set to 1, INTA is

asserted if the enable bit MREIN-

TE is set to 1.

Read/Write accessible always.

MREINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MREINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MREINTE

MII Management Read Error In-

terrupt Enable. If MREINTE is

set, the MREINT bit will be able to

set the INTR bit.

Read/Write accessible always.

MREINTE

set

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