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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C972BVCW датащи(PDF) 122 Page - Advanced Micro Devices |
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AM79C972BVCW датащи(HTML) 122 Page - Advanced Micro Devices |
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122 / 130 page  122 Am79C972 This bit was called DTCR in the LANCE (Am7990) device. Read/Write accessible only when either the STOP or the SPND bit is set. 2 LOOP Loopback Enable allows the Am79C972 controller to operate in full-duplex mode for test pur- poses. The setting of the full- duplex control bits in BCR9 have no effect when the device oper- ates in loopback mode. When LOOP = 1, loopback is enabled. In combination with INTL and MIIILP, various loopback modes are defined as follows in Table 21. Refer to Loop Back Operation section for more details. Read/Wr ite acc es sible only when either the STOP or the SPND bit is set. LOOP is cleared by H_RESET or S_RESET and is unaffected by STOP. 1 DTX Disable Transmit results in Am79C972 controller not access- ing the Transmit Descriptor Ring and, therefore, no transmissions are attempted. DTX = 0, will set TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is asserted. Read/Write accessible only when either the STOP or the SPND bit is set. 0 DRX Disable Receiver results in the Am79C972 controller not access- ing the Receive Descriptor Ring and, therefore, all receive frame data are ignored. DRX = 0, will set RXON bit (CSR0 bit 5) if STRT (CSR0 bit 1) is asserted. Read/Write accessible only when either the STOP or the SPND bit is set. CSR16: Initialization Block Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADRL This register is an alias of CSR1. Read/Write accessible only when either the STOP or the SPND bit is set. CSR17: Initialization Block Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADRH This register is an alias of CSR2. Read/Write accessible only when either the STOP or the SPND bit is set. CSR18: Current Receive Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRBAL Contains the lower 16 bits of the current receive buffer address at which the Am79C972 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR19: Current Receive Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRBAU Contains the upper 16 bits of the current receive buffer address at which the Am79C972 controller will store incoming frame data. Table 21. Loopback Configuration LOOP INTL MIIILP Function GPSI 0 0 0 Normal Operation 1 1 0 Internal Loop 1 0 0 External Loop MII 0 0 0 Normal Operation 0 0 1 Internal Loop 1 0 0 External Loop |
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