AM79C972BVCW datasheet(115/130 Pages) AMD

115 / 130 page

Am79C972

115

mode and the Am79C972 con-

troller receives a Magic Packet

frame. When MPINT is set to 1,

INTA is asserted if IENA (CSR0,

bit 6) and the enable bit MPINTE

are set to 1.

Read/Write accessible always.

MPINT is cleared by the host by

writing a 1. Writing a 0 has no af-

fect.

MPINT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MPINTE

Magic Packet Interrupt Enable. If

MPINTE is set to 1, the MPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

MPINT

cleared

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

MPEN

Magic Packet Enable. MPEN al-

lows activation of the Magic

Packet mode by the host. The

Am79C972 controller will enter

the Magic Packet mode when

both MPEN and MPMODE are

set to 1.

Read/Write accessible always.

MPEN

cleared

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

MPMODE

The Am79C972 controller will en-

ter the Magic Packet mode when

MPMODE is set to 1 and either

PG is asserted or MPEN is set to

Read/Write accessible always.

MPMODE is cleared to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit

SPND

Suspend. Setting SPND to 1 will

cause the Am79C972 controller

to start requesting entrance into

suspend mode. The host must

poll SPND until it reads back 1 to

determine that the Am79C972

controller has entered the sus-

pend mode. Setting SPND to 0

will get the Am79C972 controller

out of suspend mode. SPND can

only be set to 1 if STOP (CSR0,

bit 2) is set to 0. H_RESET,

S_RESET or setting the STOP bit

will get the Am79C972 controller

out of suspend mode.

Requesting entrance into the

suspend mode by the host de-

pends on the setting of the

FASTSPNDE bit (CSR7, bit 15).

Refer to the bit description of the

FASTSPNDE bit and the Sus-

pend section in Detailed Func-

tions, Buffer Management Unit

for details.

In suspend mode, all of the CSR

and BCR registers are accessi-

ble. As long as the Am79C972

controller is not reset while in

suspend mode (by H_RESET,

S_RESET or by setting the STOP

bit), no re-initialization of the de-

vice is required after the device

comes out of suspend mode. The

Am79C972 controller will contin-

ue at the transmit and receive de-

scriptor

ring

locations,

from

where it had left, when it entered

the suspend mode.

Read/Write accessible always.

SPND is cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-12

TLEN

Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during the Am79C972 controller

initialization. This field is written

during the Am79C972 controller

initialization routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

TLEN is only defined after initial-

ization. These bits are unaffected

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