AM79C972BVCW datasheet(78/130 Pages) AMD

78 / 130 page

Am79C972

Figure 44.

Flash Write from Expansion Bus Data Port

AMD Flash Programming

AMD’s Flash products are programmed on a byte-by-

byte basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed

by the program set-up command and data write cycles.

Addresses are latched on the falling edge of EBWE

and the data is latched on the rising edge of EBWE.

The rising edge of EBWE begins programming.

Upon executing the AMD Flash Embedded Program

Algorithm command sequence, the Am79C972 con-

troller is not required to provide further controls or tim-

ing. The AMD Flash product will compliment EBD[7]

during a read of the programmed location until the pro-

gramming is complete. The host software should poll

the programmed address until EBD[7] matches the

programmed value.

AMD Flash byte programming is allowed in any se-

quence and across sector boundaries. Note that a data

0 cannot be programmed back to a 1. Only erase oper-

ations can convert zeros to ones. AMD Flash chip

erase is a six-bus cycle operation. There are two unlock

write cycles, followed by writing the set-up command.

Two more unlock cycles are then followed by the chip

erase command. Chip erase does not require the user

to program the device prior to erasure. Upon executing

the AMD Flash Embedded Erase Algorithm command

sequence, the Flash device will program and verify the

entire memory for an all zero data pattern prior to elec-

trical erase. The Am79C972 controller is not required

to provide any controls or timings during these opera-

tions. The automatic erase begins on the rising edge of

the last EBWE pulse in the command sequence and

terminates when the data on EBD[7] is 1, at which time

the Flash device returns to the read mode. Polling by

the Am79C972 controller is not required during the

erase sequence. The following FLASH programming-

table excerpt (Table 9) shows the command sequence

for byte programming and sector/chip erasure on an

AMD Flash device. In the following table, PA and PD

stand for programmed address and programmed data,

and SA stands for sector address.

The Am79C972 controller will support only a single

sector erase per command and not concurrent sector

erasures. The Am79C972 controller will support most

FLASH devices as long as there is no timing require-

ment between the completion of commands. The

FLASH access time cannot be guaranteed with the

Am79 C9 72 controller access me chanism. The

Am79C972 controller will also support only Flash de-

vices that do not require data hold times after write op-

erations.

EBUA_EBA[7:0]

EBD[7:0]

AS_EBOE

EROMCS

EBUA[19:16]

EBDA[15:8]

EBA[7:0]

CLK

EBWE

21485C-47

Table 9.

Am29Fxxx Flash Command

Command

Sequence

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Write Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Byte Program

5555h

AAh

2AAAh

55H

5555h

A0h

Chip Erase

5555h

AAh

2AAAh

55H

5555h

80h

5555h

AAh

2AAAh

55h

5555h

10h

Sector Erase

5555h

AAh

2AAAh

55H

5555h

80h

5555h

AAh

2AAAh

55h

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