AM79C972BVCW datasheet(66/130 Pages) AMD

66 / 130 page

Am79C972

allows simultaneous transmit and receive activity on the

TXDAT and RXDAT pins of the GPSI port, and the

TXD[3:0] and RXD[3:0] pins of the MII port. Full-duplex

operation is enabled by the FDEN bit located in BCR9

for all ports. Full-duplex operation is also enabled

through Auto-Negotiation when DANAS (BCR 32, bit 7)

is not enabled on the MII port and the ASEL bit is set,

and both the external PHY and its link partner are ca-

pable of Auto-Negotiation and full-duplex operation.

When operating in full-duplex mode, the following

changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

n The first 64 bytes of every transmit frame are not

preserved in the Transmit FIFO during transmission

of the first 512 bits as described in the Transmit Ex-

ception Conditions section. Instead, when full-du-

plex mode is active and a frame is being transmitted,

the XMTFW bits (CSR80, bits 9-8) always govern

when transmit DMA is requested.

n Successful reception of the first 64 bytes of every

receive frame is not a requirement for Receive DMA

to begin as described in the Receive Exception Con-

ditions section. Instead, receive DMA will be re-

quested as soon as either the RCVFW threshold

(CSR80, bits 12-13) is reached or a complete valid

receive frame is detected, regardless of length. This

Receive FIFO operation is identical to when the RPA

bit (CSR124, bit 3) is set during half-duplex mode

operation.

The MAC engine changes for full-duplex operation are

as follows:

n Changes to the Transmit Deferral mechanism:

— Transmission is not deferred while receive is

active.

— The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits

is started when transmit activity for the first

packet ends, instead of when transmit and car-

rier activity ends.

n The 4.0 µs carrier sense blinding period after a

transmission during which the SQE test normally

occurs is disabled.

n The collision indication input to the MAC engine is

ignored.

The MII changes for full-duplex operation are as fol-

lows:

n The collision detect (COL) pin is disabled.

n The SQE test function is disabled.

n Loss of Carrier (LCAR) reporting is disabled.

Full-Duplex Link Status LED Support

The Am79C972 controller provides bits in each of the

LED Status registers (BCR4, BCR5, BCR6, BCR7) to

display the Full-Duplex Link Status. If the FDLSE bit (bit

8) is set, a value of 1 will be sent to the associated LED-

OUT bit when in Full-Duplex.

AM79C972BVCW датащи(PDF) 66 Page - Advanced Micro Devices

AM79C972BVCW датащи(HTML) 66 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL