AM79C972BVCW datasheet(20/130 Pages) AMD

20 / 130 page

Am79C972

be used to drive external logic that switches the device

power source from the main power supply to an auxil-

iary power supply.

TBC_EN

Time Base Clock Enable

Input

TBC_EN is an input that controls the selection of the

source of the Time Base Clock. The Time Base Clock

is used in loading the EEPROM, generation of the

PHY_RST, and the timing of the MDC and MDIO sig-

nals. When the input to this pin is LOW, an internal free

running oscillator with a maximum frequency of 20

MHz is used. When the input to this pin is HIGH, the

TBC_IN pin input is used to inject externally generated

clock into the device. For typical applications which will

use the internal oscillation, this pin should be tied to

ground.

When RST is active, TBC_EN is an input for NAND tree

testing.

TBC_IN

Time Base Clock Input

Input

TBC_IN may be used to connect to an external clock

source to drive the internal circuitry that loads the

EEPROM and controls the MDC and MDIO signals.

This input is selected when the TBC_EN pin is HIGH.

This pin should be tied to ground when the TBC_EN pin

is LOW.

PHY_RST

PHY Reset

Output

PHY_RST is an output pin that is used to reset the ex-

ternal PHY. This output eliminates the need for a fan

out buffer for the PCI RST signal, provides polarity for

the specific PHY used, and prevents the resetting of

the PHY when the PG input is LOW. The output polarity

is determined by the RST_POL bit(CSR116, bit0).

EEPROM Interface

EECS

EEPROM Chip Select

Output

This pin is designed to directly interface to a serial EE-

PROM that uses the 93C46 EEPROM interface proto-

col. EECS is connected to the EEPROM’s chip select

pin. It is controlled by either the Am79C972 controller

during command portions of a read of the entire EE-

PROM, or indirectly by the host system by writing to

BCR19, bit 2.

EEDI

EEPROM Data In

Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EEDI is connected to the EEPROM’s data input

pin. It is controlled by either the Am79C972 controller

during command portions of a read of the entire

EEPROM, or indirectly by the host system by writing to

BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0 pin.

EEDO

EEPROM Data Out

Input

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EEDO is connected to the EEPROM’s data out-

put pin. It is controlled by either the Am79C972

controller during command portions of a read of the en-

tire EEPROM, or indirectly by the host system by read-

ing from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3,

MIIRXFRTGD, and SRD pins.

EESK

EEPROM Serial Clock

Input/Output

This pin is designed to directly interface to a serial

EEPROM that uses the 93C46 EEPROM interface pro-

tocol. EESK is connected to the EEPROM’s clock pin.

It is controlled by either the Am79C972 controller di-

rectly during a read of the entire EEPROM, or indirectly

by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1 and

SFBD pins.

The EESK pin is also used during EEPROM Auto-

Detection to determine whether or not an EEPROM is

present at the Am79C972 controller interface. At the

rising edge of the last CLK edge while RST is asserted,

EESK is sampled to determine the value of the EEDET

bit in BCR19. A sampled HIGH value means that an

EEPROM is present, and EEDET will be set to 1. A

sampled LOW value means that an EEPROM is not

present, and EEDET will be set to 0. See the EEPROM

Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull

up or pull down resistor must be attached instead to re-

solve the EEDET setting.

WARNING: The input signal level of EESK must be

valid for correct EEPROM detection before the

deassertion of RST.

Expansion Bus Interface

EBUA_EBA[7:0]

Expansion Bus Upper Address/

Expansion Bus Address [7:0]

Output

The EBUA_EBA[7:0] pins provide the least and most

significant bytes of address on the Expansion Bus. The

most significant address byte (address bits [19:16] dur-

ing boot device accesses) is valid on these pins at the

beginning of a boot device access, at the rising edge of

AS_EBOE. This upper address byte must be stored ex-

AM79C972BVCW датащи(PDF) 20 Page - Advanced Micro Devices

AM79C972BVCW датащи(HTML) 20 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL