AM79C972BVCW datasheet(113/130 Pages) AMD

113 / 130 page

Am79C972

113

Writing a 1 to UNIT will clear

UNITCMD and stop interrupts.

Read/Write accessible always.

UINTCMD

cleared

H_RESET or S_RESET or by

setting the STOP bit.

UINT

User Interrupt. UINT is set by the

Am79C972 controller after the

host has issued a user interrupt

command by setting UINTCMD

(CSR4, bit 7) to 1.

Read/Write accessible always.

UINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

UINT

cleared

H_RESET or S_RESET or by

setting the STOP bit.

RCVCCO

Receive Collision Counter Over-

flow is set by the Am79C972 con-

troller when the Receive Collision

Counter (CSR114 and CSR115)

has wrapped around.

When RCVCCO is set, INTA is

asserted if IENA is 1 and the

mask bit RCVCCOM is 0.

Read/Write accessible always.

RCVCCO is cleared by the host

by writing a 1. Writing a 0 has no

effect. RCVCCO is cleared by

H_RESET, S_RESET, or by set-

ting the STOP bit.

RCVCCOM Receive Collision Counter Over-

flow Mask. If RCVCCOM is set,

the RCVCCO bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

RCVCCOM

set

H_RESET or S_RESET and is

not affected by the STOP bit.

TXSTRT

Transmit Start status is set by the

Am79C972 controller whenever it

begins transmission of a frame.

When TXSTRT is set, INTA is as-

serted if IENA is 1 and the mask

bit TXSTRTM is 0.

Read/Write accessible always.

TXSTRT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

TXSTRT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

TXSTRTM

Transmit

Start

Mask.

TX-

STRTM is set, the TXSTRT bit

will be masked and unable to set

the INTR bit.

Read/Write accessible always.

TXSTRTM

set

H_RESET or S_RESET and is

not affected by the STOP bit.

1-0

RES

Reserved locations. Written as

zeros and read as undefined.

CSR5: Extended Control and Interrupt 1

Certain bits in CSR5 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR5 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

TOKINTD

Transmit OK Interrupt Disable. If

TOKINTD is set to 1, the TINT bit

in CSR0 will not be set when a

transmission

was

successful.

Only a transmit error will set the

TINT bit.

TOKINTD has no effect when

LTINTEN (CSR5, bit 14) is set to

1. A transmit descriptor with

LTINT set to 1 will always cause

TINT to be set to 1, independent

of the success of the transmis-

sion.

Read/Write accessible always.

TOKINTD

cleared

H_RESET or S_RESET and is

unaffected by STOP.

LTINTEN

Last Transmit Interrupt Enable.

When set to 1, the LTINTEN bit

will cause the Am79C972 control-

ler to read bit 28 of TMD1 as

LTINT. The setting LTINT will de-

termine if TINT will be set at the

end of the transmission.

AM79C972BVCW датащи(PDF) 113 Page - Advanced Micro Devices

AM79C972BVCW датащи(HTML) 113 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL