AM79C972BVCW datasheet(112/130 Pages) AMD

112 / 130 page

112

Am79C972

should write a 0 to this bit and

should treat the read value as un-

defined.

CSR4: Test and Features Control

Certain bits in CSR4 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR4 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

RES

Reserved location. It is OK for

legacy software to write a 1 to this

location. This bit must be set

back to 0 before setting INIT or

STRT bits.

Read/Write accessible always.

This bit is cleared by H_RESET

or S_RESET and is unaffected by

the STOP bit.

DMAPLUS

Writing and reading from this bit

has no effect. DMAPLUS is al-

ways set to 1.

RES

Reserved Location. Written as

zero and read as undefined.

TXDPOLL

Disable Transmit Polling. If TXD-

POLL is set, the Buffer Manage-

ment Unit will disable transmit

polling. Likewise, if TXDPOLL is

cleared, automatic transmit poll-

ing is enabled. If TXDPOLL is set,

TDMD bit in CSR0 must be set in

order to initiate a manual poll of a

transmit descriptor. Transmit de-

scriptor polling will not take place

if TXON is reset. Transmit polling

will take place following Receive

activities.

Read/Write accessible always.

TXDPOLL

cleared

H_RESET or S_RESET and is

unaffected by the STOP bit.

APAD_XMT Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to extend

them to 64 bytes including FCS.

The FCS is calculated for the en-

tire frame, including pad, and ap-

pended

after

the

pad

field.

APAD_XMT will override the pro-

gramming of the DXMTFCS bit

(CSR15,

bit

and

the

ADD_FCS bit (TMD1, bit 29) for

frames shorter than 64 bytes.

Read/Write accessible always.

APAD_XMT

cleared

H_RESET or S_RESET and is

unaffected by the STOP bit.

ASTRP_RCV Auto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

Read/Write accessible always.

ASTRP_RCV

cleared

H_RESET or S_RESET and is

unaffected by the STOP bit.

MFCO

Missed Frame Counter Overflow

is set by the Am79C972 control-

ler

when

the

Missed

Frame

Counter (CSR112 and CSR114)

has wrapped around.

When MFCO is set, INTA is as-

serted if IENA is 1 and the mask

bit MFCOM is 0.

Read/Write accessible always.

MFCO is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MFCO

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MFCOM

Missed Frame Counter Overflow

Mask. If MFCOM is set, the

MFCO bit will be masked and un-

able to set the INTR bit.

Read/Write accessible always.

MFCOM is set to 1 by H_RESET

or S_RESET and is not affected

by the STOP bit.

UINTCMD

User

Interrupt

Command.

UINTCMD can be used by the

host to generate an interrupt un-

related to any network activity.

When UINTCMD is set, INTA is

asserted if IENA is set to 1.

AM79C972BVCW датащи(PDF) 112 Page - Advanced Micro Devices

AM79C972BVCW датащи(HTML) 112 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL