AM79C30AVC datasheet(96/101 Pages) AMD

96 / 101 page

Am79C30A/32A Data Sheet

APPENDIX B

KEY DESIGN HINTS

FOR THE DSC/IDC CIRCUIT

Due to the high level of integration of the Am79C30A/

32A DSC/IDC circuit, it is easy to overlook important

design information when reading the data sheet. The

following list of key design hints has been compiled to

streamline the design process. A comprehensive se-

ries of ISDN application notes and tutorials is available

from AMD; please contact an AMD sales office or fac-

tory for current information.

•

The AREF pint

must be used to bias the AINA and

AINB inputs. There is a datasheet parameter, Vios,

which states that the analog inputs must be biased

to within 5 mV of AREF. AREF is

nominally 2.4 V;

normal device-to-device variation will exceed the

5-mV Vios specification. If a voltage other than

AREF is used, transmission performance at very

low signal levels will be degraded.

•

The recommended method of biasing the AINA and

AINB inputs is to use a 15–100 Kohm resistor be-

tween the input and AREF. The signal source

should be AC-coupled to the analog input. Take

care that the RC formed by the biasing resistor and

blocking capacitor does not distort the input signal.

•

The AREF output must not be loaded with a capac-

itor since it may cause the internal buffer amplifier to

become unstable. For some applications involving

significant gain external to the DSC circuit, the

AREF output may require a simple RC noise filter.

In this case, the AREF output should be isolated

from the capacitor by a resistance of greater than 1

Kohm to ensure stability.

•

The analog gain selection value (in MMR3) should

be written before the MAP is enabled.

•

The MAP auto-zero function (MMR2) should be en-

abled before the MAP is enabled.

•

The DSC/IDC circuit should be provided with de-

coupling capacitors, situated as close as possible to

the package power leads. In general, 0.1-µF ce-

ramic capacitors are sufficient, but bulk decoupling

capacitors will be required if the LS1 and LS2 loud-

speaker outputs are driving a heavy load.

•

The DSC/IDC circuit is constructed on a single sub-

strate, and therefore the device power pins must not

be from separate supplies. If there is a DC offset be-

tween the analog and digital power-supply pins, ex-

cessive current m ay flow through the device

substrate.

•

The LS1, LS2, EAR1, and EAR2 outputs are in-

tended to be used differentially. Although it is possi-

ble to use only a single output, the rejection of

power-supply noise and internal digital noise is im-

proved if the outputs are used differentially.

•

Observe the maximum loading specification for the

Ls and EAR outputs. When used differentially, the

EAr outputs must see a minimum of 540 ohms be-

tween them. Similarly, the LS outputs must see a

minimum of 40 ohms. The maximum capacitive

loading in either case is 100 pF.

•

The LS and EAR outputs need not be matched to

the load. The LS and EAR outputs are voltage driv-

ers and do not assume the presence of any partic-

ular load impedance. If the maximum loading

specification is met, the LS and EAR outputs will

function satisfactorily. In some cases, an external

resistor may be used to center the desired output

volume—for instance, while driving a 150-ohm ear-

piece with the EAR outputs.

•

If using an EAR or LS output in a single-ended fash-

ion, AC-couple the pin to the load. If not, the exces-

sive DC current will cause signal distortion.

•

When using programmable gains and filters in the

MAP, consider the dynamic range effects such as

truncation error and clipping. In case of questions in

any particular application, please contact the AMD

applications staff for assistance.

•

All MAP tone generators are referenced with re-

spect to the +3-dBm0 overload voltage—that is, a

0-dB tone yields a +3-dBm0 output. Take care to

avoid clipping when adding tones to signals as, for

example, when generating DTMF waveforms.

•

The RC connected to CAP1/CAP2 must be situated

as close as possible to the DSC circuit package to

reduce the amount of noise coupled in from other

signal traces.

•

Observe the XTAL2 frequency accuracy require-

ment of 12.288 MHz ± 80 ppm. Since crystals from

different manufacturers will vary, the DSC circuit os-

cillator output frequency at the MCLK pin must be

measured and, if necessary, the value of the crystal

load capacitors should be adjusted as part of the ini-

tial design procedure. An application note of oscilla-

tor considerations is available from AMD (ISDN

Systems Engineering Application Note, order

#12557).

•

If driving the XTAL2 pin with the external oscillator,

it is necessary to observe the datasheet input volt-

age and rise/fall time requirements. Note that the

XTAL2 levels are not TTL-compatible.

•

Take care in board layout of the DSC circuit, as with

any sensitive analog device. An application note of

DSC circuit board layout hints is available from AMD

(ISDN Systems Engineering Application Note,

order #12557).

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