AM79C30AVC datasheet(42/101 Pages) AMD

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Am79C30A/32A Data Sheet

Transmit Address Register — (TAR) — Read/Write

Address = Indirect 83H

This register contains the address of the packet to be transmitted if the TAR bit is enabled (DMR1 bit 2).

First Received Byte Address Register — (FRAR1–FRAR4) — Read/Write

Address = Indirect FRAR1–FRAR3 = 81H, FRAR4 = 8CH

These registers contain the value to match against the first byte of the incoming address. If DMR1 bits 4–7 are dis-

abled, these registers are ignored.

Second Received Byte Address Register — (SRAR1–SRAR4) — Read/Write

Address = Indirect SRAR1–SRAR3 = 82H, SRAR4 = 8DH

These registers contain the value to match against the first byte of the incoming address. If DMR1 bits 4–7 are dis-

abled, these registers are ignored.

D-Channel Receive Byte Count Register — (DRCR) — Read

Address = Indirect 89H

This register determines the maximum number of bytes in a received packet.

D-Channel Receive Byte Limit Register — (DRLR) — Read/Write

Address = Indirect 84H

This register contains the total number of received bytes.

D-Channel Transmit Byte Count Register — (DTCR) — Read/Write

Address = Indirect 85H

This register contains the total number of transferred bytes.

Random Number Generator Register — (RNGR1, RNGR2) — Read/Write

Address = Indirect RNGR1 = 8AH, RNGR2 = 8BH

These registers control the operation of the Random Number Generator. When read, they display the random num-

ber generated by the chip.

D-Channel Transmit Buffer Register — (DCTB) —Write

D-channel transmit FIFO.

D-Channel Receive Buffer Register — (DCRB) — Read

D-channel receive FIFO.

D-Channel Mode Register 1 — (DMR1) — Read/Write

Address = Indirect 86H

DMR1 controls the enable/disable options for the DLC. It is under sole control of the microprocessor and does not

generate any interrupts. DMR1 is defined in Table 39.

Table 39.

D-Channel Mode Register 1

Bit

Logical 1

Logical 0

Enable D-channel Transmit Threshold interrupt (see IR bit 0)

Disable interrupt (default value)

Enable D-channel Receive Threshold interrupt (see IR bit 1)

Disable interrupt (default value)

Enable Transmit Address Register

Disable Transmit Address Register (default value)

Enable End of Receive Packet interrupt (see DSR1 bit 1)

Disable interrupt (default value)

Enable FRAR1/SRAR1

Disable FRAR1/SRAR1 (default value)

Enable FRAR2/SRAR2

Disable FRAR2/SRAR2 (default value)

Enable FRAR3/SRAR3

Disable FRAR3/SRAR3 (default value)

Enable FRAR4/SRAR4

Disable FRAR4/SRAR4

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