AM79C30AVC datasheet(24/101 Pages) AMD

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Am79C30A/32A Data Sheet

Main Audio Processor (MAP)

(Am79C30A only)

Overview

The MAP, as illustrated in Figure 3, implements au-

dio-band analog-to-digital (ADC) and digital-to-analog

(DAC) conversions together with a wide variety of audio

support functions. Analog interfaces are provided for a

handset earpiece, a handset mouthpiece, a micro-

phone, and a loudspeaker. A programmable analog

preamplifier is included in front of the A/D converter.

The codec and filter functions are implemented using

digital signal processing (DSP) techniques to provide

operational stability and programmable features. There

is one programmable digital gain stage in the transmit

path and two in the receive path to allow precise signal

level control. Sidetone attenuation is programmable,

and programmable equalization filters are present in

both the receive and transmit paths in order to modify

the frequency response of either or both paths. Tone

generation capability is included to allow generation of

ringing signals, DTMF tones, and call progress signals.

MAP operation is described in detail in the following

sections.

Audio Inputs

The audio input port consists of two inputs (AINA and

AINB) which are selectable, one at a time, by register

programming. Signals applied to these inputs must be

AC-coupled.

Earpiece and Loudspeaker Drivers

The earpiece and loudspeaker drivers each consist of

amplifiers with differential, low-impedance outputs. The

MAP receive path signal may be routed to either of

these outputs, or to both outputs simultaneously. Alter-

natively, the MAP receive path may be routed to the

EAR outputs while the Secondary Tone Ringer (STR)

is routed to the LS outputs. The EAR drivers can drive

loads Š130 ohms between the EAR1 and EAR2 pins,

while the LS drivers can drive loads Š40 ohms between

the LS1 and LS2 pins. The maximum capacitive-load-

ing between EAR1 and EAR2 or between LS1 and LS2

is 100 pF. The EAR outputs are high-impedance when

the MAP is disabled. The LS outputs are high imped-

ance when both the MAP and the Secondary Tone

Ringer are disabled.

CAP1

CAP2

AINA

AINB

AREF

GA*

ADC

Decimators, BPF

Digital

Loopback 1

Analog

Sidetone

Gain*

(A)

DTMF

GEN.

PEAKX

GX*

COMP*

Ba channel

MUX

Transmitter

Receiver

Sidetone

Gain*

Loopback 2

Digital

EAR1

EAR2

LS1

LS2

DAC

STR*

Interpolators, LPF

GER*

GR*

EXP*

Ba channel

from

MUX

PEAKR

Tone*

Ringer

Tone*

Gen.

(B)

(C)

Notes:

Minimum

Default

Maximum

Step

0 dB**

0 dB

12 dB

0.5 dB

GER

–10 dB**

0 dB

18 dB

0.5 dB

–12 dB**

0 dB

0.5 dB

STG

–18 dB**

–18 dB

0 dB

0.5 dB

0 dB

24 dB

6.0 dB

ASTG

–27 dB**

–6 dB

1.5 dB

*Programmable

**These registers can also be programmed for infinite attenuation to break the signal path if desired.

Figure 3.

Main Audio Processor Block Diagram

09893H-4

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