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AM79C30AVC датащи(PDF) 51 Page - Advanced Micro Devices |
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AM79C30AVC датащи(HTML) 51 Page - Advanced Micro Devices |
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51 / 101 page ![]() Am79C30A/32A Data Sheet 51 MASTER Mode DSC is the timing master (FSC and SCLK are outputs) and control master (can communicate with down- stream devices). The configuration of timing master and control slave is covered within this mode. The pres- ence of the TIC bus provides D and C/I0 access to all downstream devices. For control slave applications, the DSC can disable all IOM-2 channel 1 communica- tions. DSC Downstream Downstream #1 #2 SBOUT SBIN DD DU DD DU B1, B2, D, MON0, C/10, IC1, IC2, MON1, C/I1, S/G(out), TIC(in) upstream downstream Figure 8. IOM-2 Master Mode Operation |
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