AM79C30AVC datasheet(38/101 Pages) AMD

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Am79C30A/32A Data Sheet

Table 38.

.Address Recognition

If DMR4 bit 6 is set to a logical 0, bit 1 of the FRARs is

ignored when matching the first incoming address byte.

If DMR4 bit 6 is set to a logical 1, all bits of the FRARs

are used when matching the first incoming address

byte. FRAR bit 1 is analogous to the C/R bit defined by

the CCITT recommendations. The address recognition

mechanism for the four FRAR/SRAR addresses can be

individually enabled/disabled via DMR1 bits 4–7.

First Received Byte-Only Address Recognition

If DMR4 bit 5 is set to a logical 1 and DMR4 bit 7 is set

to a logical 0, only the first byte of the incoming address

is compared with the values stored in the enabled

FRARs. An interrupt is generated if there is an address

match and the Valid Address interrupt is enabled. If the

address matches, the packet will be received.

Second Received Byte-Only Address Recognition

If DMR4 bits 5 and 7 are set to a logical 1, the DLC

compares only the value in the second byte of the in-

coming address with values stored in the enabled

SRARs. An interrupt is generated if there is an address

match and the Valid Address interrupt is enabled. If the

address matches, the packet will be received.

2-Byte Address Recognition

If DMR4 bit 5 is set to a logical 0, the first byte of the

incoming address is compared with the values stored in

the enabled FRARs, and the second byte of the incom-

ing address is compared with the value stored in the

corresponding SRAR. An interrupt is generated if a

match is found for both incoming address bytes with a

FRAR/SRAR pair and the Valid Address interrupt is en-

abled. If the address matches, the packet will be re-

ceived.

Disabling Address Recognition

If DMR1 bits 4, 5, 6, and 7 are all set to logical 0, all ad-

dress recognition is disabled and all addresses are rec-

ognized and received. In this case, the Am79C30A/32A

receives the first two bytes following the opening flag

(the incoming address), and then issues an End of Ad-

dress interrupt if the End of Address interrupt is enabled.

DLC Operation

DLC Transmit and Receive FIFOs

The DLC Transmit and Receive FIFOs may be config-

ured to the Normal or Extended mode of operation.Nor-

mal mode is fully backwards compatible with the

Revision D or prior DSC circuit, and is activated upon

RESET or if EFCR bit 0 is programmed to logical 0. In

Normal mode the Transmit and Receive FIFOs are

each 8 bytes in length.

The Extended mode of FIFO operation may be activated

by programming EFCR bit 0 to a logical 1, increasing the

depth of the Transmit and Receive FIFOs to 16 bytes

and 32 bytes, respectively. The setting of EFCR bit 0 to

logical 1 also alters the available programmable FIFO

threshold values set by DMR4 bits 2 and 3.

Receiving D-Channel Packets

The receiver controls the flow of D-channel data to the

D-channel Receive buffer and the termination of a re-

ceive packet. Up to two packets can be contained in the

D-channel Receive buffer.

After receiving an opening flag (a bit sequence of

01111110) and one byte of data which is not an abort

or flag on the D channel, the DLC sets the Packet-Re-

ception-in-Progress status bit (bit 2) in D-channel Sta-

tus Register 1 (DSR1). The DLC then receives the first

two bytes (the two address bytes). If address recogni-

tion is enabled, the Am79C30A/32A issues a Valid Ad-

dress interrupt if a match between the programmed

values and the received address is detected. If no

match is detected and address recognition is enabled,

the DLC ignores the packet. If address recognition is

DMR4

DMR1

Type of address recognition

Bit 7

Bit 5

Bits

7654

FRAR1

First received byte-only address

FRAR3

FRAR4

SRAR1

Second received byte-only address

SRAR2

SRAR3

SRAR4

FRAR1:SRAR1

2-byte address

FRAR2:SRAR2

FRAR3:SRAR3

FRAR4:SRAR4

Address recognition disabled

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